A 3.6pJ/b 56Gb/s 4-PAM receiver with 6-Bit TI-SAR ADC and quarter-rate speculative 2-tap DFE in 32 nm CMOS.
Hazar YuekselLukas KullAndreas BurgMatthias BraendliPeter BuchmannPier Andrea FranceseChristian MenolfiMarcel A. KosselThomas MorfToke Meyer AndersenDanny LuuThomas ToiflPublished in: ESSCIRC (2015)
Keyphrases
- analog to digital converter
- decision feedback
- high speed
- nm technology
- random access memory
- received signal
- power consumption
- synthetic aperture radar
- cmos technology
- low cost
- low power
- power supply
- image sensor
- error propagation
- analog vlsi
- sar images
- image reconstruction
- single chip
- soft decision
- cmos image sensor
- wireless sensor networks