A 5.7mW/Gb/s 24-to-240Ω 1.6Gb/s thin-oxide DDR transmitter with 1.9-to-7.6V/ns clock-feathering slew-rate control in 22nm CMOS.
Marcel A. KosselChristian MenolfiThomas ToiflPier Andrea FranceseMatthias BraendliPeter BuchmannLukas KullToke Meyer AndersenThomas MorfPublished in: ISSCC (2013)
Keyphrases
- rate control
- high speed
- power consumption
- power supply
- low power
- video streaming
- bit rate
- rate distortion
- rate control scheme
- rate control algorithm
- visual quality
- video coding
- video quality
- transmission electron microscopy
- cmos technology
- inter frame
- hd video
- macroblock
- congestion control
- distributed video coding
- quality control
- image quality