Romesh Kumar Nandwana

Publication Activity (10 Years)

Years Active: 2013-2023
Publications (10 Years): 17

Top Topics

Interpolation Method

Top Venues

IEEE J. Solid State Circuits

Publications

Kadaba Lakshmikumar, Alexander Kurylak, Romesh Kumar Nandwana, Bibhu Das, Joe Pampanin, Mike Brubaker, Pavan Kumar Hanumolu
A 7 pA/$\surd\text{Hz}$ Asymmetric Differential TIA for 100Gb/s PAM-4 links with -14dBm Optical Sensitivity in 16nm CMOS. ISSCC (2023)
Abhishek Bhat, Romesh Kumar Nandwana, Kadaba Lakshmikumar
An Interference Suppression Technique for Millimeter-Wave LC VCOs Using a Multiport Coupled Inductor. IEEE Trans. Circuits Syst. II Express Briefs 69 (3) (2022)
Kadaba R. Lakshmikumar, Alexander Kurylak, Romesh Kumar Nandwana, Bibhu Das, Joe Pampanin, Vito Boccuzzi, Pavan Kumar Hanumolu
High-Performance CMOS TIA for Data Center Optical Interconnects. BCICTS (2022)
Mostafa Gamal Ahmed, Dongwook Kim, Romesh Kumar Nandwana, Ahmed Elkholy, Kadaba R. Lakshmikumar, Pavan Kumar Hanumolu
A 16-Gb/s -11.6-dBm OMA Sensitivity 0.7-pJ/bit Optical Receiver in 65-nm CMOS Enabled by Duobinary Sampling. IEEE J. Solid State Circuits 56 (9) (2021)
Kadaba Lakshmikumar, Alexander Kurylak, Manohar Nagaraju, Richard Booth, Romesh Kumar Nandwana, Joe Pampanin, Vito Boccuzzi
A Process and Temperature Insensitive CMOS Linear TIA for 100 Gb/s/λ PAM-4 Optical Links. IEEE J. Solid State Circuits 54 (11) (2019)
Ahmed Elkholy, Daniel Coombs, Romesh Kumar Nandwana, Ahmed Elmallah, Pavan Kumar Hanumolu
A 2.5-5.75-GHz Ring-Based Injection-Locked Clock Multiplier With Background-Calibrated Reference Frequency Doubler. IEEE J. Solid State Circuits 54 (7) (2019)
Junheng Zhu, Romesh Kumar Nandwana, Guanghua Shu, Ahmed Elkholy, Seong Joong Kim, Pavan Kumar Hanumolu
1.82 mW 2.2 GHz PLL Using Time-Based Integral Control in 65 nm CMOS. IEEE J. Solid State Circuits 52 (1) (2017)
Mrunmay Talegaonkar, Tejasvi Anand, Ahmed Elkholy, Amr Elshazly, Romesh Kumar Nandwana, Saurabh Saxena, Brian Young, Woo-Seok Choi, Pavan Kumar Hanumolu
A 5GHz Digital Fractional-N PLL Using a 1-bit Delta-Sigma Frequency-to-Digital Converter in 65 nm CMOS. IEEE J. Solid State Circuits 52 (9) (2017)
Daniel Coombs, Ahmed Elkholy, Romesh Kumar Nandwana, Ahmed Elmallah, Pavan Kumar Hanumolu
8.6 A 2.5-to-5.75GHz 5mW 0.3psrms-jitter cascaded ring-based digital injection-locked clock multiplier in 65nm CMOS. ISSCC (2017)
Saurabh Saxena, Guanghua Shu, Romesh Kumar Nandwana, Mrunmay Talegaonkar, Ahmed Elkholy, Tejasvi Anand, Woo-Seok Choi, Pavan Kumar Hanumolu
A 2.8 mW/Gb/s, 14 Gb/s Serial Link Transceiver. IEEE J. Solid State Circuits 52 (5) (2017)
Romesh Kumar Nandwana, Saurabh Saxena, Ahmed Elkholy, Mrunmay Talegaonkar, Junheng Zhu, Woo-Seok Choi, Ahmed Elmallah, Pavan Kumar Hanumolu
29.6 A 3-to-10Gb/s 5.75pJ/b transceiver with flexible clocking in 65nm CMOS. ISSCC (2017)
Romesh Kumar Nandwana, Saurabh Saxena, Amr Elshazly, Kartikeya Mayaram, Pavan Kumar Hanumolu
A 1-to-2048 Fully-Integrated Cascaded Digital Frequency Synthesizer for Low Frequency Reference Clocks Using Scrambling TDC. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2017)
Junheng Zhu, Makrand Mahalley, Guanghua Shu, Woo-Seok Choi, Romesh Kumar Nandwana, Ahmed Elkholy, Bibhudatta Sahoo, Pavan Kumar Hanumolu
A 45-75MHz 197-452µW oscillator with 164.6dB FoM and 2.3psrms period jitter in 65nm CMOS. CICC (2017)
Braedon Salz, Mrunmay Talegaonkar, Guanghua Shu, Ahmed Elmallah, Romesh Kumar Nandwana, Bibhudatta Sahoo, Pavan Kumar Hanumolu
A 0.7V time-based inductor for fully integrated low bandwidth filter applications. CICC (2017)
Ahmed Elkholy, Saurabh Saxena, Romesh Kumar Nandwana, Amr Elshazly, Pavan Kumar Hanumolu
A 2.0-5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL With Extended Range Multi-Modulus Divider. IEEE J. Solid State Circuits 51 (8) (2016)
Guanghua Shu, Woo-Seok Choi, Saurabh Saxena, Seong Joong Kim, Mrunmay Talegaonkar, Romesh Kumar Nandwana, Ahmed Elkholy, Da Wei, Timir Nandi, Pavan Kumar Hanumolu
23.1 A 16Mb/s-to-8Gb/s 14.1-to-5.9pJ/b source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS. ISSCC (2016)
Junheng Zhu, Romesh Kumar Nandwana, Guanghua Shu, Ahmed Elkholy, Seong Joong Kim, Pavan Kumar Hanumolu
19.8 A 0.0021mm2 1.82mW 2.2GHz PLL using time-based integral control in 65nm CMOS. ISSCC (2016)
Ahmed Elkholy, Saurabh Saxena, Romesh Kumar Nandwana, Amr Elshazly, Pavan Kumar Hanumolu
A 4mW wide bandwidth ring-based fractional-n DPLL with 1.9psrms integrated-jitter. CICC (2015)
Romesh Kumar Nandwana, Tejasvi Anand, Saurabh Saxena, Seong Joong Kim, Mrunmay Talegaonkar, Ahmed Elkholy, Woo-Seok Choi, Amr Elshazly, Pavan Kumar Hanumolu
A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method. IEEE J. Solid State Circuits 50 (4) (2015)
Seong Joong Kim, Romesh Kumar Nandwana, Qadeer Khan, Robert C. N. Pilawa-Podgurski, Pavan Kumar Hanumolu
A 4-Phase 30-70 MHz Switching Frequency Buck Converter Using a Time-Based Compensator. IEEE J. Solid State Circuits 50 (12) (2015)
Saurabh Saxena, Guanghua Shu, Romesh Kumar Nandwana, Mrunmay Talegaonkar, Ahmed Elkholy, Tejasvi Anand, Seong Joong Kim, Woo-Seok Choi, Pavan Kumar Hanumolu
A 2.8mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS. VLSIC (2015)
Seong Joong Kim, Romesh Kumar Nandwana, Qadeer Ahmad Khan, Robert C. N. Pilawa-Podgurski, Pavan Kumar Hanumolu
4-phase time-based buck converter consuming 3μA/MHz quiescent current in 65nm CMOS. ISSCC (2015)
Mrunmay Talegaonkar, Tejasvi Anand, Ahmed Elkholy, Amr Elshazly, Romesh Kumar Nandwana, Saurabh Saxena, Brian Young, Woo-Seok Choi, Pavan Kumar Hanumolu
A 4.4-5.4GHz digital fractional-N PLL using ΔΣ frequency-to-digital converter. VLSIC (2014)
Saurabh Saxena, Romesh Kumar Nandwana, Pavan Kumar Hanumolu
A 5 Gb/s Energy-Efficient Voltage-Mode Transmitter Using Time-Based De-Emphasis. IEEE J. Solid State Circuits 49 (8) (2014)
Romesh Kumar Nandwana, Tejasvi Anand, Saurabh Saxena, Seong Joong Kim, Mrunmay Talegaonkar, Ahmed Elkholy, Woo-Seok Choi, Amr Elshazly, Pavan Kumar Hanumolu
A 4.25GHz-4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement. VLSIC (2014)
Saurabh Saxena, Romesh Kumar Nandwana, Pavan Kumar Hanumolu
A 5 Gb/s 3.2 mW/Gb/s 28 dB loss-compensating pulse-width modulated voltage-mode transmitter. CICC (2013)