C
search
search
reviewers
reviewers
feeds
feeds
assignments
assignments
settings
logout
8.6 A 2.5-to-5.75GHz 5mW 0.3psrms-jitter cascaded ring-based digital injection-locked clock multiplier in 65nm CMOS.
Daniel Coombs
Ahmed Elkholy
Romesh Kumar Nandwana
Ahmed Elmallah
Pavan Kumar Hanumolu
Published in:
ISSCC (2017)
Keyphrases
</>
power consumption
clock gating
nm technology
low power
high speed
cmos technology
mixed signal
power reduction
metal oxide semiconductor
clock frequency
circuit design
power dissipation
power supply
hd video
floating point
cmos image sensor
hardware implementation
face detection