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An iPWM Line-Coding-Based Wireline Transceiver With Clock -Domain Encoding for Compensating Up To 27-dB Loss While Operating at 0.5-to-0.9 V and 3-to-16 Gb/s in 65-nm CMOS.

Ashwin RamachandranYusang ChunMohamed MegahedTejasvi Anand
Published in: IEEE J. Solid State Circuits (2020)
Keyphrases
  • high speed
  • power consumption
  • low cost
  • low power
  • decoding process
  • cmos technology
  • frequency response
  • signal to noise ratio
  • error propagation
  • power supply
  • arithmetic coding
  • clock gating