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Runtime Programmable and Memory Bandwidth Optimized FPGA-Based Coprocessor for Deep Convolutional Neural Network.
Nimish Shah
Paragkumar Chaudhari
Kuruvilla Varghese
Published in:
IEEE Trans. Neural Networks Learn. Syst. (2018)
Keyphrases
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convolutional neural network
memory bandwidth
face detection
level parallelism
instruction set
low cost
application specific
general purpose
floating point
neural network
massively parallel
hardware implementation
processing units
object detection
parallel programming