FPGA Based Reconfigurable Coprocessor for Deep Convolutional Neural Network Training.
Sajna Remi ClereSachin SethumadhavanKuruvilla VarghesePublished in: DSD (2018)
Keyphrases
- neural network training
- deep learning
- hardware implementation
- field programmable gate array
- neural network
- training algorithm
- smart camera
- deep belief networks
- massively parallel
- unsupervised feature learning
- optimization method
- low cost
- application specific
- restricted boltzmann machine
- hardware architecture
- parallel computing
- particle swarm optimisation
- back propagation
- artificial neural networks
- linear combination
- particle swarm optimizer
- optimal solution
- data sets