A scalable low power issue queue for large instruction window processors.
Rajesh VivekanandhamBharadwaj S. AmruturR. GovindarajanPublished in: ICS (2006)
Keyphrases
- low power
- power consumption
- low cost
- signal processor
- high speed
- instruction set
- single chip
- high power
- power reduction
- wireless transmission
- digital signal processing
- low power consumption
- vlsi architecture
- gate array
- mixed signal
- vlsi circuits
- parallel processing
- logic circuits
- real time
- cmos technology
- parallel algorithm
- delay insensitive
- signal processing