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A 100MHz to 1GHz, 0.35V to 1.5V Supply 256 x 64 SRAM Block Using Symmetrized 9T SRAM Cell with Controlled Read.
Satish Anand Verkila
Siva Kumar Bondada
Bharadwaj S. Amrutur
Published in:
VLSI Design (2008)
Keyphrases
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power consumption
high speed
low power
data transmission
random access memory
cmos technology
clock frequency
real time
feature vectors
wireless sensor networks
low cost
data acquisition
kullback leibler divergence
low voltage
power reduction
leakage current