An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS.
Sriram R. VangalJason HowardGregory RuhlSaurabh DigheHoward WilsonJames W. TschanzDavid FinanArvind P. SinghTiju JacobShailendra JainVasantha ErraguntlaClark RobertsYatin HoskoteNitin BorkarShekhar BorkarPublished in: IEEE J. Solid State Circuits (2008)
Keyphrases
- high speed
- silicon on insulator
- cmos technology
- single chip
- ibm power processor
- parallel processing
- massively parallel
- low power
- nm technology
- power consumption
- metal oxide semiconductor
- random access memory
- low cost
- power management
- cmos image sensor
- embedded dram
- chip design
- analog vlsi
- instruction set
- dynamic random access memory
- low voltage
- parallel architectures
- image sensor
- computer architecture
- power dissipation
- power supply
- circuit design
- fine grained
- x ray
- real time