Yu-Tsun Chien

Publication Activity (10 Years)

Years Active: 1999-2007
Publications (10 Years): 0

Publications

Yu-Tsun Chien, Dong Chen, Jea-Hong Lou, Gin-Kou Ma, Rob A. Rutenbar, Tamal Mukherjee
Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters CoRR (2007)
Yu-Tsun Chien, Dong Chen, Jea-Hong Lou, Gin-Kou Ma, Rob A. Rutenbar, Tamal Mukherjee
Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters. DATE (2005)
Chua-Chin Wang, Ya-Hsin Hsueh, Yu-Tsun Chien, Ying-Pei Chen
Design of an Inter-plane Circuit for Clocked PLAs. VLSI Design 2002 (4) (2002)
Chua-Chin Wang, Cheng-Fa Tsai, Yu-Tsun Chien
Pattern Recognitin by High-Capacity Polynomial Bidirectional Hetero-Associative Network. J. Inf. Sci. Eng. 17 (2) (2001)
Chua-Chin Wang, Yu-Tsun Chien, Ying-Pei Chen
Design of an inter-plane circuit for clocked PLAs. ISCAS (2000)
Chua-Chin Wang, Yu-Tsun Chien, Ying-Pei Chen
A Practical Load-optimized VCO Design for Low-jitter 5V 500 MHz Digital Phase-locked Loop. VLSI Design 2000 (2) (2000)
Chua-Chin Wang, Yu-Tsun Chien, Ying-Pei Chen
A practical load-optimized VCO design for low-jitter 5 V 500 MHz digital phase-locked loop. ISCAS (2) (1999)