A practical load-optimized VCO design for low-jitter 5 V 500 MHz digital phase-locked loop.

Chua-Chin Wang Yu-Tsun Chien Ying-Pei Chen

Published in: ISCAS (2) (1999)

Keyphrases

phase locked loop
case study
load balancing
expert systems
training set
computational intelligence
high speed
mathematical model
high frequency
design principles