An Area-Efficient Iterative Single-Precision Floating-Point Multiplier Architecture for FPGA.
Sunwoong KimRob A. RutenbarPublished in: ACM Great Lakes Symposium on VLSI (2019)
Keyphrases
- floating point
- instruction set
- floating point arithmetic
- sparse matrices
- hardware implementation
- square root
- fixed point
- real time
- dedicated hardware
- hardware design
- hardware architecture
- signal processing
- floating point unit
- fpga implementation
- interval arithmetic
- pipelined architecture
- hardware architectures
- parallel architecture
- software implementation
- field programmable gate array
- sufficient conditions
- data management
- pairwise