Hardware implementation of MRF map inference on an FPGA platform.
Jungwook ChoiRob A. RutenbarPublished in: FPL (2012)
Keyphrases
- hardware implementation
- map inference
- markov random field
- graphical models
- dual decomposition
- reconfigurable hardware
- field programmable gate array
- parallel architecture
- signal processing
- fpga implementation
- image labeling
- hardware design
- dedicated hardware
- efficient implementation
- software implementation
- maximum a posteriori
- higher order
- hardware architecture
- belief propagation
- graph cuts
- semantic segmentation
- image processing algorithms
- fpga device
- fpga technology
- energy minimization
- random fields
- pipelined architecture
- computer vision
- xilinx virtex
- general purpose processors
- cutting plane algorithm
- cutting plane
- image segmentation
- real time
- map estimation
- integer programming
- energy function
- lp relaxation
- conditional random fields
- segmentation algorithm
- bayesian networks