ASIC Accelerator in 28 nm for the Post-Quantum Digital Signature Scheme XMSS.
Prashanth MohanWen WangBernhard JungkRuben NiederhagenJakub SzeferKen MaiPublished in: ICCD (2020)
Keyphrases
- digital signature scheme
- signature scheme
- integrated circuit
- quantum computing
- quantum computation
- application specific
- hardware implementation
- parallel implementation
- design methodology
- quantum inspired
- single chip
- physical design
- data mining
- quantum mechanics
- channel capacity
- field programmable gate array
- low power
- probability ranking principle
- quantum evolutionary algorithm
- general purpose