Wen Wang

Publication Activity (10 Years)

Years Active: 2016-2024
Publications (10 Years): 22

Top Topics

Embedded Systems

Fpga Implementation

Extended Abstract

Top Venues

IACR Cryptol. ePrint Arch.

IACR Trans. Cryptogr. Hardw. Embed. Syst.

Publications

Sejun Kim, Wen Wang, Duhyeong Kim, Adish Vartak, Michael Steiner, Rosario Cammarota
Towards a Polynomial Instruction Based Compiler for Fully Homomorphic Encryption Accelerators. IACR Cryptol. ePrint Arch. 2024 (2024)
Jingwei Hu, Wen Wang, Kris Gaj, Donglong Chen, Huaxiong Wang
Universal Gaussian elimination hardware for cryptographic purposes. J. Cryptogr. Eng. 14 (2) (2024)
Jingwei Hu, Wen Wang, Kris Gaj, Liping Wang, Huaxiong Wang
Engineering Practical Rank-Code-Based Cryptographic Schemes on Embedded Hardware. A Case Study on ROLLO. IEEE Trans. Computers 72 (7) (2023)
Jianan Mu, Yi Ren, Wen Wang, Yizhong Hu, Shuai Chen, Chip-Hong Chang, Junfeng Fan, Jing Ye, Yuan Cao, Huawei Li, Xiaowei Li
Scalable and Conflict-Free NTT Hardware Accelerator Design: Methodology, Proof, and Implementation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (5) (2023)
Po-Jen Chen, Tung Chou, Sanjay Deshpande, Norman Lahr, Ruben Niederhagen, Jakub Szefer, Wen Wang
Complete and Improved FPGA Implementation of Classic McEliece. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2022 (3) (2022)
Po-Jen Chen, Tung Chou, Sanjay Deshpande, Norman Lahr, Ruben Niederhagen, Jakub Szefer, Wen Wang
Complete and Improved FPGA Implementation of Classic McEliece. IACR Cryptol. ePrint Arch. 2022 (2022)
Patrick Longa, Wen Wang, Jakub Szefer
The Cost to Break SIKE: A Comparative Hardware-Based Analysis with AES and SHA-3. CRYPTO (3) (2021)
Patrick Longa, Wen Wang, Jakub Szefer
The Cost to Break SIKE: A Comparative Hardware-Based Analysis with AES and SHA-3. IACR Cryptol. ePrint Arch. 2020 (2020)
Prashanth Mohan, Wen Wang, Bernhard Jungk, Ruben Niederhagen, Jakub Szefer, Ken Mai
ASIC Accelerator in 28 nm for the Post-Quantum Digital Signature Scheme XMSS. ICCD (2020)
Changsu Kim, Yongwoo Lee, Shinnung Jeong, Wen Wang, Jakub Szefer, Hanjun Kim
Pipeline-aware Logic Deduplication in High-Level Synthesis for Post-Quantum Cryptography Algorithms. FPGA (2020)
Wen Wang, Shanquan Tian, Bernhard Jungk, Nina Bindel, Patrick Longa, Jakub Szefer
Parameterized Hardware Accelerators for Lattice-Based Cryptography and Their Application to the HW/SW Co-Design of qTESLA. IACR Cryptol. ePrint Arch. 2020 (2020)
Wen Wang, Shanquan Tian, Bernhard Jungk, Nina Bindel, Patrick Longa, Jakub Szefer
Parameterized Hardware Accelerators for Lattice-Based Cryptography and Their Application to the HW/SW Co-Design of qTESLA. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2020 (3) (2020)
Wen Wang, Bernhard Jungk, Julian Wälde, Shuwen Deng, Naina Gupta, Jakub Szefer, Ruben Niederhagen
XMSS and Embedded Systems. SAC (2019)
Shanquan Tian, Wen Wang, Jakub Szefer
Merge-Exchange Sort Based Discrete Gaussian Sampler with Fixed Memory Access Pattern. FPT (2019)
Wen Wang, Jakub Szefer, Ruben Niederhagen
FPGA-Based Niederreiter Cryptosystem Using Binary Goppa Codes. PQCrypto (2018)
Wen Wang, Bernhard Jungk, Julian Wälde, Shuwen Deng, Naina Gupta, Jakub Szefer, Ruben Niederhagen
XMSS and Embedded Systems - XMSS Hardware Accelerators for RISC-V. IACR Cryptol. ePrint Arch. 2018 (2018)
Wen Wang, Jakub Szefer, Ruben Niederhagen
Post-Quantum Cryptography on FPGAs: The Niederreiter Cryptosystem: Extended Abstract. ACM Great Lakes Symposium on VLSI (2018)
Wen Wang, Jakub Szefer, Ruben Niederhagen
FPGA-based Key Generator for the Niederreiter Cryptosystem Using Binary Goppa Codes. CHES (2017)
Wen Wang, Jakub Szefer, Ruben Niederhagen
FPGA-based Key Generator for the Niederreiter Cryptosystem using Binary Goppa Codes. IACR Cryptol. ePrint Arch. 2017 (2017)
Wen Wang, Jakub Szefer, Ruben Niederhagen
FPGA-based Niederreiter Cryptosystem using Binary Goppa Codes. IACR Cryptol. ePrint Arch. 2017 (2017)
Wen Wang, Jakub Szefer, Ruben Niederhagen
Solving large systems of linear equations over GF(2) on FPGAs. ReConFig (2016)
Sumedh Guha, Wen Wang, Shafeeq Ibraheem, Mahesh Balakrishnan, Jakub Szefer
Design and implementation of open-source SATA III core for Stratix V FPGAs. FPT (2016)