Architecture and circuit techniques for a 1.1-GHz 16-kb reconfigurable memory in 0.18-/spl mu/m CMOS.
Ken MaiRon HoElad AlonDean LiuYounggon KimDinesh PatilMark A. HorowitzPublished in: IEEE J. Solid State Circuits (2005)
Keyphrases
- high speed
- cmos technology
- analog vlsi
- spl times
- power dissipation
- low power
- power consumption
- circuit design
- low cost
- nm technology
- low voltage
- hardware implementation
- power reduction
- delay insensitive
- real time
- random access memory
- memory management
- heterogeneous computing
- design considerations
- compute intensive
- reconfigurable hardware
- vlsi circuits
- systolic array
- associative memory
- knowledge base
- analog to digital converter
- intel xeon
- clock frequency
- focal plane
- memory access
- digital signal processing
- design methodology
- memory requirements