An Inherently Secure FPGA using PUF Hardware-Entanglement and Side-Channel Resistant Logic in 65nm Bulk CMOS.
Burak ErbagciNail Etkin Can AkkayaCagri ErbagciKen MaiPublished in: ESSCIRC (2019)
Keyphrases
- low cost
- single chip
- silicon on insulator
- field programmable gate array
- hardware implementation
- chip design
- low power
- hardware architecture
- delay insensitive
- parallel hardware
- software implementation
- hardware design
- high speed
- cmos technology
- metal oxide semiconductor
- reconfigurable hardware
- power reduction
- real time
- digital circuits
- low power consumption
- circuit design
- hardware and software
- embedded systems
- image sensor
- power consumption
- dedicated hardware
- hardware architectures
- floating gate
- digital signal processing
- gate array
- asynchronous circuits
- electronic devices
- countermeasures
- application specific integrated circuits
- data acquisition
- hardware software
- fpga hardware
- nm technology
- modal logic
- programmable logic
- parallel computing
- ibm power processor
- fpga technology
- xilinx virtex
- random access memory
- clock frequency
- trusted computing
- image processing algorithms
- advanced encryption standard
- power supply
- fpga device
- logic circuits
- smart card