Building Fast, Dense, Low-Power Caches Using Erasure-Based Inline Multi-bit ECC.
Jangwoo KimHyunggyun YangMark P. McCartneyMudit BhargavaKen MaiBabak FalsafiPublished in: PRDC (2013)
Keyphrases
- low power
- low cost
- power consumption
- high speed
- low density parity check
- high power
- vlsi circuits
- low power consumption
- vlsi architecture
- single chip
- logic circuits
- wireless transmission
- nm technology
- channel coding
- error correction
- cmos technology
- mixed signal
- digital signal processing
- power reduction
- delay insensitive
- image sensor
- ultra low power