Reliability enhancement of bi-stable PUFs in 65nm bulk CMOS.
Mudit BhargavaCagla CakirKen MaiPublished in: HOST (2012)
Keyphrases
- cmos technology
- silicon on insulator
- nm technology
- metal oxide semiconductor
- image processing
- business intelligence
- power consumption
- high speed
- low power
- image enhancement
- low cost
- integrated circuit
- failure rate
- multiscale
- database
- power supply
- reliability analysis
- big data
- circuit design
- highly reliable
- information systems
- low voltage
- vlsi circuits
- genetic algorithm
- data sets
- real time