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17.1 A 0.6V 1.5GHz 84Mb SRAM design in 14nm FinFET CMOS technology.
Eric Karl
Zheng Guo
James W. Conary
Jeffrey L. Miller
Yong-Gee Ng
Satyanand Nalam
Daeyeon Kim
John Keane
Uddalak Bhattacharya
Kevin Zhang
Published in:
ISSCC (2015)
Keyphrases
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cmos technology
low power
power consumption
power dissipation
spl times
parallel processing
low voltage
high speed
low cost
mixed signal
silicon on insulator
design considerations
design methodology
digital camera
power reduction
design process
real time