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Asymmetric 6T SRAM with two-phase write and split bitline differential sensing for low voltage operation.

Satyanand NalamVikas ChandraCezary PietrzykRobert C. AitkenBenton H. Calhoun
Published in: ISQED (2010)
Keyphrases
  • low voltage
  • random access memory
  • design considerations
  • leakage current
  • power line
  • cmos technology
  • power management
  • sensor networks
  • power consumption
  • real time
  • low power
  • design process
  • learning experience