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A 32 nm High-k Metal Gate SRAM With Adaptive Dynamic Stability Enhancement for Low-Voltage Operation.
Pramod Kolar
Eric Karl
Uddalak Bhattacharya
Fatih Hamzaoglu
Henry Nho
Yong-Gee Ng
Yih Wang
Kevin Zhang
Published in:
IEEE J. Solid State Circuits (2011)
Keyphrases
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leakage current
low voltage
cmos technology
low power
power consumption
power line
design considerations
parallel processing
random access memory
electrical properties
image enhancement
high temperature
silicon dioxide
power management
wireless sensor networks
high speed
response time
digital images