Anindya Sundar Dhar

Publication Activity (10 Years)

Years Active: 1992-2024
Publications (10 Years): 61

Top Topics

Hierarchical Block Matching

Vlsi Architecture

Fault Localization

Cellular Automata

Top Venues

Circuits Syst. Signal Process.

IEEE Trans. Very Large Scale Integr. Syst.

IET Circuits Devices Syst.

Publications

Rajen Kumar Patra, Anindya Sundar Dhar
A Generalized Rearranged Coprime Array Configuration for Direction-of-Arrival Estimation with Increased Degrees of Freedom. Circuits Syst. Signal Process. 43 (9) (2024)
Ayan Palchaudhuri, Anindya Sundar Dhar
FPGA Specific Speed-Area Optimized Architectures of Arithmetic Cores with Scan Insertion for Carry Chain Based Multi-level Logic Implementation. VLSID (2024)
Rajen Kumar Patra, Anindya Sundar Dhar
A Novel Translated Coprime Array Configuration for Moving Platform in Direction-of-Arrival Estimation. Circuits Syst. Signal Process. 42 (4) (2023)
Rajen Kumar Patra, Anindya Sundar Dhar
An Improved CACIS Configuration for DOA Estimation with Enhanced Degrees of Freedom. Circuits Syst. Signal Process. 42 (3) (2023)
Rajen Kumar Patra, Anindya Sundar Dhar
Optimal Coprime Array: Properties, Optimization, and k-times extension. Circuits Syst. Signal Process. 42 (6) (2023)
Rajen Kumar Patra, Anindya Sundar Dhar
Unfolded Coprime Transformed Nested Arrays for Increased DOF and Negligible Mutual Coupling. Circuits Syst. Signal Process. 42 (12) (2023)
Rajen Kumar Patra, Anindya Sundar Dhar
Novel Moving Coprime Array Configurations for Real-Valued Sources. IEEE Signal Process. Lett. 29 (2022)
Rajen Kumar Patra, Anindya Sundar Dhar
A Novel $k$-times Extended Coprime Array for DOA Estimation With Increased Degrees of Freedom. IEEE Signal Process. Lett. 29 (2022)
Ayan Palchaudhuri, Digvijay Anand, Anindya Sundar Dhar
FPGA fabric conscious architecture design and automation of speed-area efficient Margolus neighborhood based cellular automata with variegated scan path insertion. J. Parallel Distributed Comput. 167 (2022)
Rajen Kumar Patra, Anindya Sundar Dhar
A special coprime array configuration for increased degrees of freedom. Digit. Signal Process. 122 (2022)
Avishek Sinha Roy, Hardik Agrawal, Anindya Sundar Dhar
ACBAM-Accuracy-Configurable Sign Inclusive Broken Array Booth Multiplier Design. IEEE Trans. Emerg. Top. Comput. 10 (4) (2022)
Ayan Palchaudhuri, Sandeep Sharma, Anindya Sundar Dhar
Design Automation for Tree-based Nearest Neighborhood-aware Placement of High-speed Cellular Automata on FPGA with Scan Path Insertion. ACM Trans. Design Autom. Electr. Syst. 26 (4) (2021)
Ayan Palchaudhuri, Anindya Sundar Dhar
Speed-area optimized VLSI architecture of multi-bit cellular automaton cell based random number generator on FPGA with testable logic support. J. Parallel Distributed Comput. 151 (2021)
Rajen Kumar Patra, Anindya Sundar Dhar
A Novel Nested Array for Real-Valued Sources Exploiting Array Motion. IEEE Signal Process. Lett. 28 (2021)
Ayan Banerjee, Anindya Sundar Dhar
A Novel Paradigm of CORDIC-Based FFT Architecture Framed on the Optimality of High-Radix Computation. Circuits Syst. Signal Process. 40 (1) (2021)
Avishek Sinha Roy, Anindya Sundar Dhar
SIBAM - Sign Inclusive Broken Array Multiplier Design for Error Tolerant Applications. IEEE Trans. Circuits Syst. (11) (2020)
Ayan Palchaudhuri, Sandeep Sharma, Anindya Sundar Dhar
Placement Aware Design and Automation of High Speed Architectures for Tree-Structured Linear Cellular Automata on FPGAs with Scan Path Insertion. FPGA (2020)
Ayan Palchaudhuri, Anindya Sundar Dhar
Testable Architecture Design for Programmable Cellular Automata on FPGA Using Run-Time Dynamically Reconfigurable Look-Up Tables. J. Electron. Test. 36 (4) (2020)
Avishek Sinha Roy, Rajdeep Biswas, Anindya Sundar Dhar
On Fast and Exact Computation of Error Metrics in Approximate LSB Adders. IEEE Trans. Very Large Scale Integr. Syst. 28 (4) (2020)
Ayan Palchaudhuri, Anindya Sundar Dhar
Primitive Instantiation for Speed-Area Efficient Architecture Design of Cellular Automata based Mageto Logic on FPGA with Built-In Testability. FCCM (2020)
Subrahmanyam Mula, Vinay Chakravarthi Gogineni, Anindya Sundar Dhar
Robust Proportionate Adaptive Filter Architectures Under Impulsive Noise. IEEE Trans. Very Large Scale Integr. Syst. 27 (5) (2019)
Tanmai Kulshreshtha, Anindya Sundar Dhar
Improved VLSI architecture for triangular windowed sliding DFT based on CORDIC algorithm. IET Circuits Devices Syst. 13 (2) (2019)
Atin Mukherjee, Anindya Sundar Dhar
Defect Tolerant Majority Voter Design Using Triple Transistor Redundancy. iSES (2019)
Kailash Chandra Ray, Anindya Sundar Dhar
CORDIC-Based VLSI Architectures of Running DFT with Refreshing Mechanism. J. Signal Process. Syst. 91 (5) (2019)
Ayan Palchaudhuri, Anindya Sundar Dhar
VLSI Architectures for Jacobi Symbol Computation. VLSI Design (2019)
Ayan Palchaudhuri, Anindya Sundar Dhar
Design and automation of VLSI architectures for bidirectional scan based fault localization approach in FPGA fabric aware cellular automata topologies. J. Parallel Distributed Comput. 130 (2019)
Atin Mukherjee, Anindya Sundar Dhar
Triple transistor based triple modular redundancy with embedded voter circuit. Microelectron. J. 87 (2019)
Ayan Palchaudhuri, Anindya Sundar Dhar
Fault Localization and Testability Approaches for FPGA Fabric Aware Canonic Signed Digit Recoding Implementations. J. Electron. Test. 35 (6) (2019)
Ayan Palchaudhuri, Anindya Sundar Dhar
FPGA Fabric Conscious Design and Implementation of Speed-Area Efficient Signed Digit Add-Subtract Logic through Primitive Instantiation. ACSSC (2019)
Avishek Sinha Roy, Anindya Sundar Dhar
A Novel Approach for Fast and Accurate Mean Error Distance Computation in Approximate Adders. ISCAS (2018)
Ayan Palchaudhuri, Anindya Sundar Dhar
Redundant Binary to Two's Complement Converter on FPGAs Through Fabric Aware Scan Based Encoding Approach for Fault Localization Support. IPDPS Workshops (2018)
Subrahmanyam Mula, Vinay Chakravarthi Gogineni, Anindya Sundar Dhar
Algorithm and VLSI Architecture Design of Proportionate-Type LMS Adaptive Filters for Sparse System Identification. IEEE Trans. Very Large Scale Integr. Syst. 26 (9) (2018)
Ayan Palchaudhuri, Anindya Sundar Dhar
Fast Carry Chain Based Architectures for Two's Complement to CSD Recoding on FPGAs. ARC (2018)
Ayan Palchaudhuri, Anindya Sundar Dhar
High Speed FPGA Fabric Aware CSD Recoding with Run-Time Support for Fault Localization. VLSI Design (2018)
Kailash Chandra Ray, M. V. N. V. Prasad, Anindya Sundar Dhar
An Efficient VLSI Architecture for Computation of Discrete Fractional Fourier Transform. J. Signal Process. Syst. 90 (11) (2018)
Avishek Sinha Roy, Anindya Sundar Dhar
A Novel Approach for Fast and Accurate Mean Error Distance Computation in Approximate Adders. CoRR (2018)
Atin Mukherjee, Anindya Sundar Dhar
Reliable VLSI Architecture Design Using Modulo-Quad-Transistor Redundancy Method. Circuits Syst. Signal Process. 37 (12) (2018)
Tanmai Kulshreshtha, Anindya Sundar Dhar
CORDIC-Based High Throughput Sliding DFT Architecture with Reduced Error-Accumulation. Circuits Syst. Signal Process. 37 (11) (2018)
Sumantra Sarkar, Ayan Biswas, Anindya Sundar Dhar, Rahul M. Rao
Adaptive Bus Encoding for Transition Reduction on Off-Chip Buses With Dynamically Varying Switching Characteristics. IEEE Trans. Very Large Scale Integr. Syst. 25 (11) (2017)
Subrahmanyam Mula, Vinay Chakravarthi Gogineni, Anindya Sundar Dhar
Algorithm and Architecture Design of Adaptive Filters With Error Nonlinearities. IEEE Trans. Very Large Scale Integr. Syst. 25 (9) (2017)
Ayan Palchaudhuri, Anindya Sundar Dhar
Redundant Arithmetic Based High Speed Carry Free Hybrid Adders with Built-In Scan Chain on FPGAs. HiPC (2017)
Mamata Panigrahy, Nirmal Chandra Behera, B. Vandana, Indrajit Chakrabarti, Anindya Sundar Dhar
Memory Efficient Fractal-SPIHT Based Hybrid Image Encoder. VDAT (2017)
Subrahmanyam Mula, Vinay Chakravarthi Gogineni, Anindya Sundar Dhar
Algorithm/Architecture Co-design of Proportionate-type LMS Adaptive Filters for Sparse System Identification. CoRR (2017)
Amitava Ghosh, Anindya Sundar Dhar, Achintya Halder
Fraction phase based low energy frequency calibration: analysis and design. IET Circuits Devices Syst. 11 (3) (2017)
Chandrakanth Mamidala, Anindya Sundar Dhar
High-performance VLSI architectures for M-PSK modems. IET Circuits Devices Syst. 11 (2) (2017)
Tanmai Kulshreshtha, Anindya Sundar Dhar
CORDIC-based Hann windowed sliding DFT architecture for real-time spectrum analysis with bounded error-accumulation. IET Circuits Devices Syst. 11 (5) (2017)
Ayan Palchaudhuri, Amrit Anand Amresh, Anindya Sundar Dhar
Efficient Automated Implementation of Testable Cellular Automata Based Pseudorandom Generator Circuits on FPGAs. J. Cell. Autom. 12 (3-4) (2017)
Ayan Palchaudhuri, Anindya Sundar Dhar
Built-In Fault Localization Circuitry for High Performance FPGA Based Implementations. J. Electron. Test. 33 (4) (2017)
Ayan Palchaudhuri, Anindya Sundar Dhar
Primitive Instantiation Based Fault Localization Circuitry for High Performance FPGA Designs. VDAT (2017)
Atin Mukherjee, Anindya Sundar Dhar
Triple transistor based fault tolerance for resource constrained applications. Microelectron. J. 68 (2017)
Ayan Palchaudhuri, Anindya Sundar Dhar
High performance bit-sliced pipelined comparator tree for FPGAs. VDAT (2016)
Kausik Ghosh, Anindya Sundar Dhar
Erratum to: A fast VLSI architecture of a hierarchical block matching algorithm for motion estimation. J. Real Time Image Process. 11 (1) (2016)
Atin Mukherjee, Anindya Sundar Dhar
Choice of granularity for reliable circuit design using dynamic reconfiguration. Microelectron. Reliab. 63 (2016)
Rohan Mukherjee, Vikrant Mahajan, Anindya Sundar Dhar, Indrajit Chakrabarti
High Performance VISI Design of Diamond Search Algorithm for Fast Motion Estimation. J. Circuits Syst. Comput. 25 (9) (2016)
Mamata Panigrahy, Indrajit Chakrabarti, Anindya Sundar Dhar
Low-Delay Parallel Architecture for Fractal Image Compression. Circuits Syst. Signal Process. 35 (3) (2016)
Kausik Ghosh, Anindya Sundar Dhar
A fast VLSI architecture of a hierarchical block matching algorithm for motion estimation. J. Real Time Image Process. 11 (1) (2016)
Ayan Palchaudhuri, Anindya Sundar Dhar
Efficient Implementation of Scan Register Insertion on Integer Arithmetic Cores for FPGAs. VLSI Design (2016)
Avishek Sinha Roy, N. Prasad, Anindya Sundar Dhar
Approximate conditional carry adder for error tolerant applications. VDAT (2016)
Rohan Mukherjee, Keyur Sheth, Anindya Sundar Dhar, Indrajit Chakrabarti, Somnath Sengupta
High Performance VLSI Architecture for Three-Step Search Algorithm. Circuits Syst. Signal Process. 34 (5) (2015)
Atin Mukherjee, Anindya Sundar Dhar
New triple-transistor based defect-tolerant systems for reliable digital architectures. ISCAS (2015)
Atin Mukherjee, Anindya Sundar Dhar
Real-time fault-tolerance with hot-standby topology for conditional sum adder. Microelectron. Reliab. 55 (3-4) (2015)
Mamata Panigrahy, Indrajit Chakrabarti, Anindya Sundar Dhar
VLSI design of fast fractal image encoder. VDAT (2014)
Kailash Chandra Ray, Anindya Sundar Dhar
CORDIC-Based VLSI Architecture for Implementing Kaiser-Bessel Window in Real Time Spectral Analysis. J. Signal Process. Syst. 74 (2) (2014)
Amitava Ghosh, Anindya Sundar Dhar, Achintya Halder
An ultra low power MICS/ISM band transmitter in 0.18 μm CMOS. VDAT (2014)
Ayan Banerjee, Anindya Sundar Dhar
Pipelined VLSI Architecture using CORDIC for Transform Domain Equalizer. J. Signal Process. Syst. 70 (1) (2013)
Nilanjan Chattaraj, Anindya Sundar Dhar
Random Access Analog Memory (RA2M) for Video Signal Application. VLSI Design (2012)
Amitava Ghosh, Achintya Halder, Anindya Sundar Dhar
A Variable RF Carrier Modulation Scheme for Ultralow Power Wireless Body-Area Network. IEEE Syst. J. 6 (2) (2012)
Atin Mukherjee, Anindya Sundar Dhar
Design of a Self-Reconfigurable Adder for Fault-Tolerant VLSI Architecture. ISED (2012)
Atin Mukherjee, Anindya Sundar Dhar
Design of a Fault-Tolerant Conditional Sum Adder. VDAT (2012)
Ashis Kumar Mal, Om Prakash Hari, Rishi Todani, Anindya Sundar Dhar
Design of DXT architecture using current switched integrator. APCCAS (2010)
Kaushik Bhattacharyya, Rakesh Biswas, Anindya Sundar Dhar, Swapna Banerjee
Architectural design and FPGA implementation of radix-4 CORDIC processor. Microprocess. Microsystems 34 (2-4) (2010)
C. Thakkar, Anindya Sundar Dhar
Sampled analog architecture for 2-D DCT. ISCAS (2006)
Ayan Banerjee, Anindya Sundar Dhar
Novel architecture for QAM modulator-demodulator and its generalization to multicarrier modulation. Microprocess. Microsystems 29 (7) (2005)
Mrityunjoy Chakraborty, Anindya Sundar Dhar, Moon Ho Lee
A trigonometric formulation of the LMS algorithm for realization on pipelined CORDIC. IEEE Trans. Circuits Syst. II Express Briefs (9) (2005)
Arindam Basu, Anindya Sundar Dhar
Design Issues in Switched Capacitor Ladder Filters. VLSI Design (2005)
Ashis Kumar Mal, Arindam Basu, Anindya Sundar Dhar
Sampled analog architecture for DCT and DST. ISCAS (2) (2004)
Ashis Kumar Mal, Anindya Sundar Dhar
Analog VLSI Architecture for Discrete Cosine Transform using Dynamic Switched Capacitors. VLSI Design (2004)
Arindam Basu, Ashis Kumar Mal, Anindya Sundar Dhar
Digital controlled analog architecture for DCT and DST using capacitor switching. ISCAS (2) (2004)
Ashis Kumar Mal, Anindya Sundar Dhar
Analog sampled data architecture for discrete Hartley transform for prime N. ICECS (2003)
Ayan Banerjee, Anindya Sundar Dhar, Swapna Banerjee
FPGA realization of a CORDIC based FFT processor for biomedical signal processing. Microprocess. Microsystems 25 (3) (2001)
Mrityunjoy Chakraborty, Anindya Sundar Dhar, Suraiya Pervin
CORDIC realization of the transversal adaptive filter using a trigonometric LMS algorithm. ICASSP (2001)
Mrityunjoy Chakraborty, Suraiya Pervin, Anindya Sundar Dhar
Systolizing the adaptive decision feedback equalizer using a symbolic state space formulation. EUSIPCO (2000)
Anindya Sundar Dhar
An Array Architecture for Computing KLT Basis Vectors. VLSI Design (1992)