Erratum to: A fast VLSI architecture of a hierarchical block matching algorithm for motion estimation.
Kausik GhoshAnindya Sundar DharPublished in: J. Real Time Image Process. (2016)
Keyphrases
- algorithm for motion estimation
- hierarchical block matching
- vlsi architecture
- motion estimation
- low complexity
- block matching
- low power
- vlsi implementation
- motion vectors
- motion compensation
- real time
- video coding
- inter frame
- motion model
- video compression
- motion compensated
- phase correlation
- motion field
- image sequences
- computational complexity
- video sequences
- computer vision
- spatial domain
- rate distortion
- super resolution
- optical flow
- power consumption
- motion parameters
- prediction error
- image data
- reference frame
- compressed domain
- block size
- moving objects