Kailash Chandra Ray

Publication Activity (10 Years)

Years Active: 2008-2024
Publications (10 Years): 34

Top Topics

Cardiac Arrhythmias

Wavelet Transform

Vlsi Architecture

Top Venues

IEEE Trans. Instrum. Meas.

J. Signal Process. Syst.

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Vivek Singh, Kailash Chandra Ray, Somanath Tripathy
An Efficient Method and Hardware System for Monitoring of Illegal Logging Events in Forest. IEEE Syst. J. 18 (1) (2024)
Satyam Shukla, Utkarsh, Md Azam, Kailash Chandra Ray
An Efficient Fault-Tolerant Instruction Decoder for RISC-V Based Dual-Core Soft-Processors. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (12) (2023)
Satyam Shukla, Punyesh Kumar Jha, Kailash Chandra Ray
An energy-efficient single-cycle RV32I microprocessor for edge computing applications. Integr. 88 (2023)
Pritiranjan Khatua, Kailash Chandra Ray
VLSI Architecture of DCT-Based Harmonic Wavelet Transform for Time-Frequency Analysis. IEEE Trans. Instrum. Meas. 72 (2023)
Pritiranjan Khatua, Kailash Chandra Ray
VLSI Architecture of Modified Complex Harmonic Wavelet Transform. Circuits Syst. Signal Process. 42 (12) (2023)
Pritiranjan Khatua, Kailash Chandra Ray
An Efficient DCT-II Based Harmonic Wavelet Transform for Time-Frequency Analysis. J. Signal Process. Syst. 94 (12) (2022)
Garima Sahu, Kailash Chandra Ray
An Efficient Method for Detection and Localization of Myocardial Infarction. IEEE Trans. Instrum. Meas. 71 (2022)
Satyam Shukla, Kailash Chandra Ray
A Low-Overhead Reconfigurable RISC-V Quad-Core Processor Architecture for Fault-Tolerant Applications. IEEE Access 10 (2022)
Pritiranjan Khatua, Kailash Chandra Ray
A Low Computational Complexity Modified Complex Harmonic Wavelet Transform. Circuits Syst. Signal Process. 41 (11) (2022)
Garima Sahu, Akanksha Gupta, Kailash Chandra Ray
An Efficient Signal Processing Technique for Automated Cardiovascular Disease Detection. iSES (2022)
Rakesh Palisetty, Amit Kumar Panda, Kailash Chandra Ray
ASIC Implementation of Low PAPR Multidevice Variable-Rate Architecture for IEEE 802.11ah. IEEE Trans. Instrum. Meas. 70 (2021)
Amit Kumar Panda, Rakesh Palisetty, Kailash Chandra Ray
High-Speed Area-Efficient VLSI Architecture of Three-Operand Binary Adder. IEEE Trans. Circuits Syst. (11) (2020)
Rakesh Palisetty, Kailash Chandra Ray
Multiuser Variable Rate GO-OFDMA Architecture and Its FPGA Prototype. IEEE Syst. J. 14 (2) (2020)
Amit Kumar Panda, Kailash Chandra Ray
A Coupled Variable Input LCG Method and its VLSI Architecture for Pseudorandom Bit Generation. IEEE Trans. Instrum. Meas. 69 (4) (2020)
Amit Kumar Panda, Rakesh Palisetty, Kailash Chandra Ray
Area-Efficient Parallel-Prefix Binary Comparator. iSES (2019)
Satyam Shukla, Kailash Chandra Ray
Design and ASIC Implementation of a Reconfigurable Fault-Tolerant ALU for Space Applications. iSES (2019)
Akash Agarwal, Vibhooti Kumar Sinha, Rakesh Palisetty, Preetam Kumar, Kailash Chandra Ray, Kamlesh Kumar, Tulika Pandey
Performance Analysis and FPGA Prototype of Variable Rate GO-OFDMA Baseband Transmission Scheme. Wirel. Pers. Commun. 108 (2) (2019)
Kailash Chandra Ray, Anindya Sundar Dhar
CORDIC-Based VLSI Architectures of Running DFT with Refreshing Mechanism. J. Signal Process. Syst. 91 (5) (2019)
Garima Sahu, Kailash Chandra Ray
An Efficient Signal Processing Technique for Automated Myocardial Infarction Detection. iSES (2019)
Pritiranjan Khatua, Kailash Chandra Ray
A Basis Function for DCT Based Discrete Orthogonal S-Transform. iSES (2019)
Vivek Singh, Kailash Chandra Ray, Somanath Tripathy
Blind Detection and Classification Algorithm for Smart Audio Monitoring System. iSES (2019)
Amit Kumar Panda, Kailash Chandra Ray
Modified Dual-CLCG Method and its VLSI Architecture for Pseudorandom Bit Generation. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2019)
Rakesh Palisetty, Kailash Chandra Ray
FPGA Prototype and Real Time Analysis of Multiuser Variable Rate CI-GO-OFDMA. IEEE Trans. Instrum. Meas. 67 (3) (2018)
Sandeep Raj, Kailash Chandra Ray
Sparse representation of ECG signals for automated recognition of cardiac arrhythmias. Expert Syst. Appl. 105 (2018)
Kailash Chandra Ray, M. V. N. V. Prasad, Anindya Sundar Dhar
An Efficient VLSI Architecture for Computation of Discrete Fractional Fourier Transform. J. Signal Process. Syst. 90 (11) (2018)
Sandeep Raj, Kailash Chandra Ray
A Personalized Point-of-Care Platform for Real-Time ECG Monitoring. IEEE Trans. Consumer Electron. 64 (4) (2018)
Sandeep Raj, Kailash Chandra Ray
Automated recognition of cardiac arrhythmias using sparse decomposition over composite dictionary. Comput. Methods Programs Biomed. 165 (2018)
Sandeep Raj, Kailash Chandra Ray
Application of variational mode decomposition and ABC optimized DAG-SVM in arrhythmia analysis. ISED (2017)
Vikas Kumar, Kailash Chandra Ray, Preetam Kumar
A VLSI architecture of CORDIC-based popular windows and its FPGA prototype. Int. J. High Perform. Syst. Archit. 7 (2) (2017)
Sandeep Raj, Kailash Chandra Ray
ECG Signal Analysis Using DCT-Based DOST and PSO Optimized SVM. IEEE Trans. Instrum. Meas. 66 (3) (2017)
Don Kurian Dennis, Ayushi Priyam, Sukhpreet Singh Virk, Sajal Agrawal, Tanuj Sharma, Arijit Mondal, Kailash Chandra Ray
Single cycle RISC-V micro architecture processor and its FPGA prototype. ISED (2017)
Sandeep Raj, Kailash Chandra Ray, Om Shankar
Cardiac arrhythmia beat classification using DOST and PSO tuned SVM. Comput. Methods Programs Biomed. 136 (2016)
K. K. Soundra Pandian, Kailash Chandra Ray
Dynamic Hash key-based stream cipher for secure transmission of real time ECG signal. Secur. Commun. Networks 9 (17) (2016)
Piyush Sharma, Kailash Chandra Ray
Efficient methodology for electrocardiogram beat classification. IET Signal Process. 10 (7) (2016)
Amit Kumar Panda, Kailash Chandra Ray
FPGA Prototype of Low Latency BBS PRNG. iNIS (2015)
K. K. Soundra Pandian, Kailash Chandra Ray
Non-singular sequence folding-based pseudorandom key generation algorithm for cryptographic processor. Secur. Commun. Networks 8 (18) (2015)
Sandeep Raj, G. S. S. Praveen Chand, Kailash Chandra Ray
ARM-based arrhythmia beat monitoring system. Microprocess. Microsystems 39 (7) (2015)
Arun Kumar Singh, Madhav Kumar Singh, Kailash Chandra Ray
Design and Implementation of Quadruple Floating-Point CORDIC. iNIS (2015)
K. K. Soundra Pandian, Kailash Chandra Ray
Five decade evolution of feedback shift register: algorithms, architectures and applications. Int. J. Commun. Networks Distributed Syst. 15 (2/3) (2015)
Rohit Shukla, Kailash Chandra Ray
Low Latency Hybrid CORDIC Algorithm. IEEE Trans. Computers 63 (12) (2014)
Kailash Chandra Ray, Anindya Sundar Dhar
CORDIC-Based VLSI Architecture for Implementing Kaiser-Bessel Window in Real Time Spectral Analysis. J. Signal Process. Syst. 74 (2) (2014)
Saptadeep Pal, K. K. Soundra Pandian, Kailash Chandra Ray
FPGA implementation of stream cipher using Toeplitz Hash function. ICACCI (2014)
Vikas Kumar, Kailash Chandra Ray, Preetam Kumar
CORDIC-based VLSI architecture for real time implementation of flat top window. Microprocess. Microsystems 38 (8) (2014)
Vinay Gautam, Kailash Chandra Ray, Pauline C. Haddow
Hardware efficient design of Variable Length FFT Processor. DDECS (2011)
Kailash Chandra Ray, A. S. Dhar
High Throughput VLSI Architecture for Blackman Windowing in Real Time Spectral Analysis. J. Comput. 3 (5) (2008)