An Efficient Fault-Tolerant Instruction Decoder for RISC-V Based Dual-Core Soft-Processors.
Satyam Shukla UtkarshMd AzamKailash Chandra RayPublished in: IEEE Trans. Circuits Syst. I Regul. Pap. (2023)
Keyphrases
- fault tolerant
- instruction set
- fault tolerance
- distributed systems
- application specific
- floating point
- embedded systems
- state machine
- computer architecture
- load balancing
- level parallelism
- parallel processing
- general purpose
- memory access
- parallel algorithm
- computer systems
- high performance computing
- parallel computing
- high availability
- mobile agent system
- memory hierarchy
- multi agent systems