FPGA Fabric Conscious Design and Implementation of Speed-Area Efficient Signed Digit Add-Subtract Logic through Primitive Instantiation.
Ayan PalchaudhuriAnindya Sundar DharPublished in: ACSSC (2019)
Keyphrases
- efficient implementation
- implementation issues
- hardware architecture
- hardware design
- high speed
- real time
- design process
- hardware implementation
- micron cmos
- parallel distributed
- hardware architectures
- fpga technology
- fpga implementation
- fpga device
- reconfigurable hardware
- chip design
- case study
- current status
- logic circuits
- classical logic
- design considerations
- field programmable gate array
- low cost