Ayan Palchaudhuri

Publication Activity (10 Years)

Years Active: 2012-2024
Publications (10 Years): 20

Top Topics

Cellular Automata

Nearest Neighborhood

Top Venues

J. Electron. Test.

J. Parallel Distributed Comput.

Publications

Ayan Palchaudhuri, Anindya Sundar Dhar
FPGA Specific Speed-Area Optimized Architectures of Arithmetic Cores with Scan Insertion for Carry Chain Based Multi-level Logic Implementation. VLSID (2024)
Ayan Palchaudhuri, Digvijay Anand, Anindya Sundar Dhar
FPGA fabric conscious architecture design and automation of speed-area efficient Margolus neighborhood based cellular automata with variegated scan path insertion. J. Parallel Distributed Comput. 167 (2022)
Ayan Palchaudhuri, Sandeep Sharma, Anindya Sundar Dhar
Design Automation for Tree-based Nearest Neighborhood-aware Placement of High-speed Cellular Automata on FPGA with Scan Path Insertion. ACM Trans. Design Autom. Electr. Syst. 26 (4) (2021)
Ayan Palchaudhuri, Anindya Sundar Dhar
Speed-area optimized VLSI architecture of multi-bit cellular automaton cell based random number generator on FPGA with testable logic support. J. Parallel Distributed Comput. 151 (2021)
Ayan Palchaudhuri, Sandeep Sharma, Anindya Sundar Dhar
Placement Aware Design and Automation of High Speed Architectures for Tree-Structured Linear Cellular Automata on FPGAs with Scan Path Insertion. FPGA (2020)
Ayan Palchaudhuri, Anindya Sundar Dhar
Testable Architecture Design for Programmable Cellular Automata on FPGA Using Run-Time Dynamically Reconfigurable Look-Up Tables. J. Electron. Test. 36 (4) (2020)
Ayan Palchaudhuri, Anindya Sundar Dhar
Primitive Instantiation for Speed-Area Efficient Architecture Design of Cellular Automata based Mageto Logic on FPGA with Built-In Testability. FCCM (2020)
Ayan Palchaudhuri, Anindya Sundar Dhar
VLSI Architectures for Jacobi Symbol Computation. VLSI Design (2019)
Ayan Palchaudhuri, Anindya Sundar Dhar
Design and automation of VLSI architectures for bidirectional scan based fault localization approach in FPGA fabric aware cellular automata topologies. J. Parallel Distributed Comput. 130 (2019)
Ayan Palchaudhuri, Anindya Sundar Dhar
Fault Localization and Testability Approaches for FPGA Fabric Aware Canonic Signed Digit Recoding Implementations. J. Electron. Test. 35 (6) (2019)
Ayan Palchaudhuri, Anindya Sundar Dhar
FPGA Fabric Conscious Design and Implementation of Speed-Area Efficient Signed Digit Add-Subtract Logic through Primitive Instantiation. ACSSC (2019)
Ayan Palchaudhuri, Anindya Sundar Dhar
Redundant Binary to Two's Complement Converter on FPGAs Through Fabric Aware Scan Based Encoding Approach for Fault Localization Support. IPDPS Workshops (2018)
Ayan Palchaudhuri, Anindya Sundar Dhar
Fast Carry Chain Based Architectures for Two's Complement to CSD Recoding on FPGAs. ARC (2018)
Ayan Palchaudhuri, Anindya Sundar Dhar
High Speed FPGA Fabric Aware CSD Recoding with Run-Time Support for Fault Localization. VLSI Design (2018)
Ayan Palchaudhuri, Anindya Sundar Dhar
Redundant Arithmetic Based High Speed Carry Free Hybrid Adders with Built-In Scan Chain on FPGAs. HiPC (2017)
Ayan Palchaudhuri, Amrit Anand Amresh, Anindya Sundar Dhar
Efficient Automated Implementation of Testable Cellular Automata Based Pseudorandom Generator Circuits on FPGAs. J. Cell. Autom. 12 (3-4) (2017)
Ayan Palchaudhuri, Anindya Sundar Dhar
Built-In Fault Localization Circuitry for High Performance FPGA Based Implementations. J. Electron. Test. 33 (4) (2017)
Ayan Palchaudhuri, Anindya Sundar Dhar
Primitive Instantiation Based Fault Localization Circuitry for High Performance FPGA Designs. VDAT (2017)
Ayan Palchaudhuri, Anindya Sundar Dhar
High performance bit-sliced pipelined comparator tree for FPGAs. VDAT (2016)
Ayan Palchaudhuri, Anindya Sundar Dhar
Efficient Implementation of Scan Register Insertion on Integer Arithmetic Cores for FPGAs. VLSI Design (2016)
Ayan Palchaudhuri, Rajat Subhra Chakraborty, Durga Prasad Sahoo
Automated Design of High Performance Integer Arithmetic Cores on FPGA. DSD (2015)
Ayan Palchaudhuri, Rajat Subhra Chakraborty, Mohammad Salman, Sreemukh Kardas, Debdeep Mukhopadhyay
Highly Compact Automated Implementation of Linear CA on FPGAs. ACRI (2014)
Rajat Subhra Chakraborty, Indrasish Saha, Ayan Palchaudhuri, Gowtham Kumar Naik
Hardware Trojan Insertion by Direct Modification of FPGA Configuration Bitstream. IEEE Des. Test 30 (2) (2013)
Sanjay Burman, Ayan Palchaudhuri, Rajat Subhra Chakraborty, Debdeep Mukhopadhyay, Pranav Singh
Effect of Malicious Hardware Logic on Circuit Reliability. VDAT (2012)