FPGA Specific Speed-Area Optimized Architectures of Arithmetic Cores with Scan Insertion for Carry Chain Based Multi-level Logic Implementation.
Ayan PalchaudhuriAnindya Sundar DharPublished in: VLSID (2024)
Keyphrases
- micron cmos
- high speed
- hardware implementation
- general purpose processors
- general purpose
- fpga hardware
- real time
- software implementation
- application specific integrated circuits
- fpga technology
- efficient implementation
- domain specific
- hardware design
- floating point
- fpga implementation
- hardware architectures
- logic programming
- high level
- design methodologies
- real time image processing
- reconfigurable hardware
- pipelined architecture
- signal processing