Sign in
Efficient Implementation of Scan Register Insertion on Integer Arithmetic Cores for FPGAs.
Ayan Palchaudhuri
Anindya Sundar Dhar
Published in:
VLSI Design (2016)
Keyphrases
</>
efficient implementation
integer arithmetic
parallel architectures
hardware implementation
field programmable gate array
highly parallel
general purpose processors
active set
euclidean distance transform
search space