Redundant Arithmetic Based High Speed Carry Free Hybrid Adders with Built-In Scan Chain on FPGAs.

Ayan Palchaudhuri Anindya Sundar Dhar

Published in: HiPC (2017)

Keyphrases

high speed
multiple valued
programmable logic
field programmable gate array
low power
data sets
real time
frame rate
image processing
floating point
neural network
low cost
embedded systems
hardware implementation
data mining
parallel architectures
scan data
database
single scan
highly redundant
pipelined architecture