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Speed-area optimized VLSI architecture of multi-bit cellular automaton cell based random number generator on FPGA with testable logic support.
Ayan Palchaudhuri
Anindya Sundar Dhar
Published in:
J. Parallel Distributed Comput. (2021)
Keyphrases
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random number generator
cellular automaton
vlsi architecture
cellular automata
random number
high speed
shift register
real time
vlsi implementation
low power
signal processing
hardware implementation
low cost
frequency domain
low complexity