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Design of a Self-Reconfigurable Adder for Fault-Tolerant VLSI Architecture.
Atin Mukherjee
Anindya Sundar Dhar
Published in:
ISED (2012)
Keyphrases
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fault tolerant
vlsi architecture
fault tolerance
low power
vlsi implementation
distributed systems
low complexity
load balancing
power consumption
safety critical
real time
message passing
high assurance
digital libraries
multiresolution
fault isolation