Ashis Kumar Mal

Publication Activity (10 Years)

Years Active: 2003-2024
Publications (10 Years): 16

Top Topics

Auction Protocol

Top Venues

IET Circuits Devices Syst.

Wirel. Pers. Commun.

Comput. Electr. Eng.

Secur. Commun. Networks

Publications

Anu Samanta, Indranil Hatai, Ashis Kumar Mal
A Survey on Hardware Accelerator Design of Deep Learning for Edge Devices. Wirel. Pers. Commun. 137 (3) (2024)
Anu Samanta, Indranil Hatai, Ashis Kumar Mal
An energy-efficient voice activity detector using reconfigurable Gaussian base normalization deep neural network. Multim. Tools Appl. 82 (18) (2023)
Amrita Mukherjee, Pratik Chakraborty, Shankar Prakriya, Ashis Kumar Mal
Performance of Novel Adaptive Schemes for Cognitive Full-Duplex Relaying-Based Downlink Cooperative NOMA. IEEE Trans. Wirel. Commun. 22 (5) (2023)
Biswajit Ghosh, Aniruddha Chandra, Ashis Kumar Mal
Fuzzy Logic-Based Energy-Optimal Collinear DF Relay Placement in Two-Hop η -μ Fading Channel. Int. J. Wirel. Inf. Networks 29 (2) (2022)
Amrita Mukherjee, Pratik Chakraborty, Shankar Prakriya, Ashis Kumar Mal
Cooperative Mode Switching-Based Cognitive NOMA With Transmit Antenna and User Selection. IEEE Trans. Signal Inf. Process. over Networks 8 (2022)
Amrita Mukherjee, Pratik Chakraborty, Shankar Prakriya, Ashis Kumar Mal
Performance of an Adaptive Cooperative NOMA Scheme with Transmit Antenna Selection. ANTS (2021)
Debabrata Bej, Shubhranil Chakraborty, Sekh Arif Mahammad, Ashis Kumar Mal
A cost-effective alertness-rating tool to enable situational awareness among on-duty static security guards in Covid-19 pandemic. J. Reliab. Intell. Environ. 7 (4) (2021)
R. S. S. M. R. Krishna, Ashis Kumar Mal, Rajat Mahapatra
Time-Domain Smart Temperature Sensor Using Current Starved Inverters and Switched Ring Oscillator-Based Time-to-Digital Converter. Circuits Syst. Signal Process. 39 (4) (2020)
Sumalya Ghosh, Bishnu Prasad De, Kanchan Baran Maji, Rajib Kar, Durbadal Mandal, Ashis Kumar Mal
Optimal Design of Ultra-Low-Power 2.4 GHz LNA for IEEE 802.15.4/Bluetooth Applications. J. Circuits Syst. Comput. 29 (16) (2020)
R. S. S. M. R. Krishna, Ashis Kumar Mal, Rajat Mahapatra
All MOS noise-shaped time-mode temperature sensor. Integr. 65 (2019)
Sumalya Ghosh, Bishnu Prasad De, Rajib Kar, Durbadal Mandal, Ashis Kumar Mal
Optimal design of complementary metal-oxide-semiconductor analogue circuits: An evolutionary approach. Comput. Electr. Eng. 80 (2019)
Madhusmita Panda, Santosh Kumar Patnaik, Ashis Kumar Mal, Sumalya Ghosh
Fast and optimised design of a differential VCO using symbolic technique and multi objective algorithms. IET Circuits Devices Syst. 13 (8) (2019)
Sumalya Ghosh, Bishnu Prasad De, Rajib Kar, Ashis Kumar Mal
Symbiotic organisms search algorithm for optimal design of CMOS two-stage op-amp with nulling resistor and robust bias circuit. IET Circuits Devices Syst. 13 (5) (2019)
Debabrata Bej, Subhajit Rakshit, Ashis Kumar Mal, Rajat Mahapatra
A cost-effective system for triggering alarm to distracted drivers/ nurses. Comput. Electr. Eng. 76 (2019)
Madhusmita Panda, Santosh Kumar Patnaik, Ashis Kumar Mal
Performance enhancement of a VCO using symbolic modelling and optimisation. IET Circuits Devices Syst. 12 (2) (2018)
Biswajit Ghosh, Aniruddha Chandra, Ashis Kumar Mal
Optimal Location of Energy Efficient DF Relay Node in κ - μ Fading Channel. Wirel. Pers. Commun. 96 (1) (2017)
S. Choudhury, Vivek Nair, Jaydeep Howlader, B. Choudhury, Ashis Kumar Mal
An integrated routing and offset-time adaptation scheme for OBS network. ICDCN (2015)
Saurav Mandal, Ashis Kumar Mal
Analysis of resistive load ring oscillator. ReTIS (2015)
Jaydeep Howlader, Ashis Kumar Mal
Sealed-bid auction: a cryptographic solution to bid-rigging attack in the collusive environment. Secur. Commun. Networks 8 (18) (2015)
Jaydeep Howlader, Sanjit Kumar Roy, Ashis Kumar Mal
Practical Receipt-Free Sealed-Bid Auction in the Coercive Environment. IACR Cryptol. ePrint Arch. 2014 (2014)
Jaydeep Howlader, Sanjit Kumar Roy, Ashis Kumar Mal
Practical Receipt-Free Sealed-Bid Auction in the Coercive Environment. ICISC (2013)
Rishi Todani, Ashis Kumar Mal
A power efficient and digitally assisted CMOS complementary telescopic amplifier with wide input common mode range. ISQED (2013)
Jaydeep Howlader, Jayanta Kar, Ashis Kumar Mal
Coercion Resistant MIX for Electronic Auction. ICISS (2012)
Subhrabrata Choudhury, Vivek Nair, Ashis Kumar Mal
Routing Scheme for OBS Networks. JOCN 4 (10) (2012)
Ashis Kumar Mal, Om Prakash Hari, Rishi Todani, Anindya Sundar Dhar
Design of DXT architecture using current switched integrator. APCCAS (2010)
Rajib Kar, Anuran Chattaraj, Aniruddha Chandra, Ashis Kumar Mal, A. K. Bhattacharjee
Delay Estimation for On-Chip VLSI Interconnect using Weibull Distribution Function. ICIIS (2008)
Ashis Kumar Mal, Arindam Basu, Anindya Sundar Dhar
Sampled analog architecture for DCT and DST. ISCAS (2) (2004)
Ashis Kumar Mal, Arindam Basu
A generalized analog architecture for DCT, DST and its inverse. ICASSP (5) (2004)
Ashis Kumar Mal, Anindya Sundar Dhar
Analog VLSI Architecture for Discrete Cosine Transform using Dynamic Switched Capacitors. VLSI Design (2004)
Arindam Basu, Ashis Kumar Mal, Anindya Sundar Dhar
Digital controlled analog architecture for DCT and DST using capacitor switching. ISCAS (2) (2004)
Ashis Kumar Mal, Anindya Sundar Dhar
Analog sampled data architecture for discrete Hartley transform for prime N. ICECS (2003)