A fast VLSI architecture of a hierarchical block matching algorithm for motion estimation.
Kausik GhoshAnindya Sundar DharPublished in: J. Real Time Image Process. (2016)
Keyphrases
- hierarchical block matching
- algorithm for motion estimation
- vlsi architecture
- motion estimation
- low complexity
- block matching
- vlsi implementation
- low power
- motion compensation
- motion vectors
- video coding
- real time
- motion compensated
- image sequences
- optical flow
- video sequences
- motion field
- spatial domain
- computational complexity
- phase correlation
- video compression
- inter frame
- reference frame
- motion parameters
- super resolution
- rate distortion
- computer vision
- coding efficiency
- low cost
- motion model
- image processing