Shiyu Su

Publication Activity (10 Years)

Years Active: 2014-2024
Publications (10 Years): 27

Top Topics

Analog To Digital Converter

Design Automation

Top Venues

IEEE J. Solid State Circuits

Publications

Qiaochu Zhang, Hsiang-Chun Cheng, Shiyu Su, Mike Shuo-Wei Chen
Fractional-N Digital MDLL With Injection-Error Scrambling and Calibration. IEEE J. Solid State Circuits 59 (1) (2024)
Qiaochu Zhang, Hsiang-Chun Cheng, Shiyu Su, Mike Shuo-Wei Chen
A Fractional-N Digital MDLL with Injection-Error Scrambling and Background Third-Order DTC Delay Equalizer Achieving -67dBc Fractional Spur. ISSCC (2023)
Ce Yang, Shiyu Su, Mike Shuo-Wei Chen
Millimeter-Wave Receiver With Non-Uniform Time-Approximation Filter. IEEE J. Solid State Circuits 58 (5) (2023)
Hsiang-Chun Cheng, Shiyu Su, Mayank Palaria, Qiaochu Zhang, Ce Yang, Sushmit Hossain, Ryan Bena, Buyun Chen, Zerui Liu, Juzheng Liu, Rezwan Rasul, Quan Nguyen, Wei Wu, Mike Shuo-Wei Chen
A Memristor-Based Analog Accelerator for Solving Quadratic Programming Problems. CICC (2023)
Shiyu Su, Oiaochu Zhang, Mike Shuo-Wei Chen
A 2GS/s 8.5-Bit Time-Based ADC using a Segmented Stochastic Flash TDC. CICC (2023)
Mayank Palaria, Shiyu Su, Hsiang-Chun Cheng, Rezwan A. Rasul, Qiaochu Zhang, Soumya Mahapatra, Chong-Fatt Law, Sushmit Hossain, Ryan M. Bena, Wei Wu, Quan Nguyen, Mike Shuo-Wei Chen
Analog Kalman Filter with Integration and Digitization via a Shared Thyristor-Based VCO for Sensor Fusion in 65 nm CMOS. ESSCIRC (2023)
Qiaochu Zhang, Shiyu Su, Mike Shuo-Wei Chen
A cost-efficient fully synthesizable stochastic time-to-digital converter design based on integral nonlinearity scrambling. DAC (2022)
Shiyu Su, Qiaochu Zhang, Mohsen Hassanpourghadi, Juzheng Liu, Rezwan A. Rasul, Mike Shuo-Wei Chen
Analog/Mixed-Signal Circuit Synthesis Enabled by the Advancements of Circuit Architectures and Machine Learning Algorithms. ASP-DAC (2022)
Shiyu Su, Mike Shuo-Wei Chen
SAW-Less Direct RF Transmitter With Multimode Noise Shaping and Tri-Level Time-Approximation Filter. IEEE J. Solid State Circuits 57 (3) (2022)
Qiaochu Zhang, Shiyu Su, Cheng-Ru Ho, Mike Shuo-Wei Chen
A Fractional-N Digital MDLL With Background Two-Point DTC Calibration. IEEE J. Solid State Circuits 57 (1) (2022)
Shiyu Su, Qiaochu Zhang, Juzheng Liu, Mohsen Hassanpourghadi, Rezwan A. Rasul, Mike Shuo-Wei Chen
TAFA: Design Automation of Analog Mixed-Signal FIR Filters Using Time Approximation Architecture. ASP-DAC (2022)
Shiyu Su, Mike Shuo-Wei Chen
High-Speed Digital-to-Analog Converter Design Towards High Dynamic Range. CICC (2022)
Shiyu Su, Mike Shuo-Wei Chen
A Time-Approximation Filter for Direct RF Transmitter. IEEE J. Solid State Circuits 56 (7) (2021)
Shiyu Su, Qiaochu Zhang, Juzheng Liu, Mohsen Hassanpourghadi, Rezwan A. Rasul, Mike Shuo-Wei Chen
TAFA: Design Automation of Analog Mixed-Signal FIR Filters Using Time Approximation Architecture. CoRR (2021)
Shiyu Su, Qiaochu Zhang, Mohsen Hassanpourghadi, Juzheng Liu, Rezwan A. Rasul, Mike Shuo-Wei Chen
Analog/Mixed-Signal Circuit Synthesis Enabled by the Advancements of Circuit Architectures and Machine Learning Algorithms. CoRR (2021)
Juzheng Liu, Shiyu Su, Meghna Madhusudan, Mohsen Hassanpourghadi, Samuel Saunders, Qiaochu Zhang, Rezwan A. Rasul, Yaguang Li, Jiang Hu, Arvind Kumar Sharma, Sachin S. Sapatnekar, Ramesh Harjani, Anthony Levi, Sandeep Gupta, Mike Shuo-Wei Chen
From Specification to Silicon: Towards Analog/Mixed-Signal Design Automation using Surrogate NN Models with Transfer Learning. ICCAD (2021)
Qiaochu Zhang, Shiyu Su, Cheng-Ru Ho, Mike Shuo-Wei Chen
29.4 A Fractional-N Digital MDLL with Background Two-Point DTC Calibration Achieving -60dBc Fractional Spur. ISSCC (2021)
Mohsen Hassanpourghadi, Shiyu Su, Rezwan A. Rasul, Juzheng Liu, Qiaochu Zhang, Mike Shuo-Wei Chen
Circuit Connectivity Inspired Neural Network for Analog Mixed-Signal Functional Modeling. DAC (2021)
Juzheng Liu, Mohsen Hassanpourghadi, Qiaochu Zhang, Shiyu Su, Mike Shuo-Wei Chen
Transfer Learning with Bayesian Optimization-Aided Sampling for Efficient AMS Circuit Modeling. ICCAD (2020)
Shiyu Su, Mike Shuo-Wei Chen
10.2 A SAW-Less Direct-Digital RF Modulator with Tri-Level Time-Approximation Filter and Reconfigurable Dual-Band Delta-Sigma Modulation. ISSCC (2020)
Shiyu Su
Millimeter-Wave Communications with Beamforming for UAV-Assisted Railway Monitoring System. IoTaaS (2020)
Qiaochu Zhang, Shiyu Su, Juzheng Liu, Mike Shuo-Wei Chen
CEPA: CNN-based Early Performance Assertion Scheme for Analog and Mixed-Signal Circuit Simulation. ICCAD (2020)
Shiyu Su, Mike Shuo-Wei Chen
A 1-5GHz Direct-Digital RF Modulator with an Embedded Time-Approximation Filter Achieving -43dB EVM at 1024 QAM. VLSI Circuits (2019)
Shiyu Su, Mike Shuo-Wei Chen
A 16b 12GS/S single/dual-rate DAC with successive bandpass delta-sigma modulator achieving <-67dBc IM3 within DC-to-6GHz tunable passbands. ISSCC (2018)
Shiyu Su, Mike Shuo-Wei Chen
A 16-bit 12-GS/s Single-/Dual-Rate DAC With a Successive Bandpass Delta-Sigma Modulator Achieving <-67-dBc IM3 Within DC to 6-GHz Tunable Passbands. IEEE J. Solid State Circuits 53 (12) (2018)
Shiyu Su, Mike Shuo-Wei Chen
A 12-Bit 2 GS/s Dual-Rate Hybrid DAC With Pulse-Error Pre-Distortion and In-Band Noise Cancellation Achieving > 74 dBc SFDR and <-80 dBc IM3 up to 1 GHz in 65 nm CMOS. IEEE J. Solid State Circuits 51 (12) (2016)
Shiyu Su, Mike Shuo-Wei Chen
27.1 A 12b 2GS/s dual-rate hybrid DAC with pulsed timing-error pre-distortion and in-band noise Cancellation Achieving >74dBc SFDR up to 1GHz in 65nm CMOS. ISSCC (2016)
Shiyu Su, Tu-I Tsai, Praveen Kumar Sharma, Mike Shuo-Wei Chen
A 12 bit 1 GS/s Dual-Rate Hybrid DAC With an 8 GS/s Unrolled Pipeline Delta-Sigma Modulator Achieving > 75 dB SFDR Over the Nyquist Band. IEEE J. Solid State Circuits 50 (4) (2015)
Shiyu Su, Tu-I Tsai, Praveen Kumar Sharma, Mike Shuo-Wei Chen
A 12-bit hybrid DAC with 8GS/s unrolled pipeline delta-sigma modulator achieving >75dB SFDR over 500MHz in 65nm CMOS. VLSIC (2014)