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Cheng-Ru Ho
ORCID
Publication Activity (10 Years)
Years Active: 2015-2022
Publications (10 Years): 10
Top Topics
Metal Oxide Semiconductor
Inverse Halftoning
Hurst Exponent
Phase Locked Loop
Top Venues
ISSCC
IEEE J. Solid State Circuits
IEEE Trans. Circuits Syst. I Regul. Pap.
CICC
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Publications
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Qiaochu Zhang
,
Shiyu Su
,
Cheng-Ru Ho
,
Mike Shuo-Wei Chen
A Fractional-N Digital MDLL With Background Two-Point DTC Calibration.
IEEE J. Solid State Circuits
57 (1) (2022)
Qiaochu Zhang
,
Shiyu Su
,
Cheng-Ru Ho
,
Mike Shuo-Wei Chen
29.4 A Fractional-N Digital MDLL with Background Two-Point DTC Calibration Achieving -60dBc Fractional Spur.
ISSCC
(2021)
Cheng-Ru Ho
,
Mike Shuo-Wei Chen
A fractional-N digital PLL with background-dither-noise-cancellation loop achieving <-62.5dBc worst-case near-carrier fractional spurs in 65nm CMOS.
ISSCC
(2018)
Cheng-Ru Ho
,
Mike Shuo-Wei Chen
A digital frequency synthesizer with dither-assisted pulling mitigation for simultaneous DCO and reference path coupling.
ISSCC
(2018)
Tzu-Fan Wu
,
Cheng-Ru Ho
,
Mike Shuo-Wei Chen
A Flash-Based Non-Uniform Sampling ADC With Hybrid Quantization Enabling Digital Anti-Aliasing Filter.
IEEE J. Solid State Circuits
52 (9) (2017)
Cheng-Ru Ho
,
Mike Shuo-Wei Chen
A Digital PLL With Feedforward Multi-Tone Spur Cancellation Scheme Achieving <-73 dBc Fractional Spur and <-110 dBc Reference Spur in 65 nm CMOS.
IEEE J. Solid State Circuits
51 (12) (2016)
Cheng-Ru Ho
,
Mike Shuo-Wei Chen
10.5 A digital PLL with feedforward multi-tone spur cancelation loop achieving <-73dBc fractional spur and <-110dBc Reference Spur in 65nm CMOS.
ISSCC
(2016)
Cheng-Ru Ho
,
Mike Shuo-Wei Chen
Interference-induced DCO spur mitigation for digital phase locked loop in 65-nm CMOS.
ESSCIRC
(2016)
Cheng-Ru Ho
,
Mike Shuo-Wei Chen
A Fractional-N DPLL With Calibration-Free Multi-Phase Injection-Locked TDC and Adaptive Single-Tone Spur Cancellation Scheme.
IEEE Trans. Circuits Syst. I Regul. Pap.
(8) (2016)
Tzu-Fan Wu
,
Cheng-Ru Ho
,
Mike Shuo-Wei Chen
A flash-based non-uniform sampling ADC enabling digital anti-aliasing filter in 65nm CMOS.
CICC
(2015)