Mike Shuo-Wei Chen

Publication Activity (10 Years)

Years Active: 2004-2024
Publications (10 Years): 60

Top Topics

Delta Sigma Modulators

Noise Cancellation

Design Automation

Top Venues

IEEE J. Solid State Circuits

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Qiaochu Zhang, Hsiang-Chun Cheng, Shiyu Su, Mike Shuo-Wei Chen
Fractional-N Digital MDLL With Injection-Error Scrambling and Calibration. IEEE J. Solid State Circuits 59 (1) (2024)
Mike Shuo-Wei Chen, Visvesh S. Sathe, Massimo Alioto, Jae-Sun Seo, Hidehiro Shiga
Guest Editorial Introduction to the Special Section on the 2023 IEEE International Solid-State Circuits Conference (ISSCC). IEEE J. Solid State Circuits 59 (1) (2024)
Mostafa M. Ayesh, Soumya Mahapatra, Ce Yang, Mike Shuo-Wei Chen
18-to-21GHz Non-Uniform Sub-Sampling Receiver with a Non-Uniform Discrete-Time FIR Filter Achieving 42dB Blocker Rejection in 28nm CMOS. ISSCC (2024)
Mutian Zhu, Mohsen Hassanpourghadi, Qiaochu Zhang, Mike Shuo-Wei Chen, Anthony F. J. Levi, Sandeep Gupta
A Novel Multi-Objective Optimization Framework for Analog Circuit Customization. DATE (2024)
Qiaochu Zhang, Hsiang-Chun Cheng, Shiyu Su, Mike Shuo-Wei Chen
A Fractional-N Digital MDLL with Injection-Error Scrambling and Background Third-Order DTC Delay Equalizer Achieving -67dBc Fractional Spur. ISSCC (2023)
Ce Yang, Shiyu Su, Mike Shuo-Wei Chen
Millimeter-Wave Receiver With Non-Uniform Time-Approximation Filter. IEEE J. Solid State Circuits 58 (5) (2023)
Hsiang-Chun Cheng, Shiyu Su, Mayank Palaria, Qiaochu Zhang, Ce Yang, Sushmit Hossain, Ryan Bena, Buyun Chen, Zerui Liu, Juzheng Liu, Rezwan Rasul, Quan Nguyen, Wei Wu, Mike Shuo-Wei Chen
A Memristor-Based Analog Accelerator for Solving Quadratic Programming Problems. CICC (2023)
Shiyu Su, Oiaochu Zhang, Mike Shuo-Wei Chen
A 2GS/s 8.5-Bit Time-Based ADC using a Segmented Stochastic Flash TDC. CICC (2023)
Mayank Palaria, Shiyu Su, Hsiang-Chun Cheng, Rezwan A. Rasul, Qiaochu Zhang, Soumya Mahapatra, Chong-Fatt Law, Sushmit Hossain, Ryan M. Bena, Wei Wu, Quan Nguyen, Mike Shuo-Wei Chen
Analog Kalman Filter with Integration and Digitization via a Shared Thyristor-Based VCO for Sensor Fusion in 65 nm CMOS. ESSCIRC (2023)
Qiaochu Zhang, Shiyu Su, Mike Shuo-Wei Chen
A cost-efficient fully synthesizable stochastic time-to-digital converter design based on integral nonlinearity scrambling. DAC (2022)
Shiyu Su, Qiaochu Zhang, Mohsen Hassanpourghadi, Juzheng Liu, Rezwan A. Rasul, Mike Shuo-Wei Chen
Analog/Mixed-Signal Circuit Synthesis Enabled by the Advancements of Circuit Architectures and Machine Learning Algorithms. ASP-DAC (2022)
Juzheng Liu, Mohsen Hassanpourghadi, Mike Shuo-Wei Chen
Two-Step Time-Domain ADC Using Delay-Tracking Pipelined-SAR TDC with 500fs Time Step in 14nm CMOS Technology. ISSCC (2022)
Shiyu Su, Mike Shuo-Wei Chen
SAW-Less Direct RF Transmitter With Multimode Noise Shaping and Tri-Level Time-Approximation Filter. IEEE J. Solid State Circuits 57 (3) (2022)
Qiaochu Zhang, Shiyu Su, Cheng-Ru Ho, Mike Shuo-Wei Chen
A Fractional-N Digital MDLL With Background Two-Point DTC Calibration. IEEE J. Solid State Circuits 57 (1) (2022)
Juzheng Liu, Mohsen Hassanpourghadi, Mike Shuo-Wei Chen
Two-Step Time-Domain ADC With Speed and Efficiency Enhanced by the Delay-Tracking Pipelined-SAR TDC. IEEE J. Solid State Circuits 57 (12) (2022)
Shiyu Su, Qiaochu Zhang, Juzheng Liu, Mohsen Hassanpourghadi, Rezwan A. Rasul, Mike Shuo-Wei Chen
TAFA: Design Automation of Analog Mixed-Signal FIR Filters Using Time Approximation Architecture. ASP-DAC (2022)
Shiyu Su, Mike Shuo-Wei Chen
High-Speed Digital-to-Analog Converter Design Towards High Dynamic Range. CICC (2022)
Shiyu Su, Mike Shuo-Wei Chen
A Time-Approximation Filter for Direct RF Transmitter. IEEE J. Solid State Circuits 56 (7) (2021)
Rezwan A. Rasul, Mike Shuo-Wei Chen
A 128x128 SRAM Macro with Embedded Matrix-Vector Multiplication Exploiting Passive Gain via MOS Capacitor for Machine Learning Application. CICC (2021)
Shiyu Su, Qiaochu Zhang, Juzheng Liu, Mohsen Hassanpourghadi, Rezwan A. Rasul, Mike Shuo-Wei Chen
TAFA: Design Automation of Analog Mixed-Signal FIR Filters Using Time Approximation Architecture. CoRR (2021)
Mike Shuo-Wei Chen, Wei-Zen Chen, Amir Amirkhany
Session 11 Overview: Advanced Wireline Links and Techniques Wireline Subcommittee. ISSCC (2021)
Aoyang Zhang, Ce Yang, Mostafa Ayesh, Mike Shuo-Wei Chen
26.6 A 5-to-6GHz Current-Mode Subharmonic Switching Digital Power Amplifier for Enhancing Power Back-Off Efficiency. ISSCC (2021)
Shiyu Su, Qiaochu Zhang, Mohsen Hassanpourghadi, Juzheng Liu, Rezwan A. Rasul, Mike Shuo-Wei Chen
Analog/Mixed-Signal Circuit Synthesis Enabled by the Advancements of Circuit Architectures and Machine Learning Algorithms. CoRR (2021)
Mohsen Hassanpourghadi, Rezwan A. Rasul, Mike Shuo-Wei Chen
A Module-Linking Graph Assisted Hybrid Optimization Framework for Custom Analog and Mixed-Signal Circuit Parameter Synthesis. ACM Trans. Design Autom. Electr. Syst. 26 (5) (2021)
Juzheng Liu, Shiyu Su, Meghna Madhusudan, Mohsen Hassanpourghadi, Samuel Saunders, Qiaochu Zhang, Rezwan A. Rasul, Yaguang Li, Jiang Hu, Arvind Kumar Sharma, Sachin S. Sapatnekar, Ramesh Harjani, Anthony Levi, Sandeep Gupta, Mike Shuo-Wei Chen
From Specification to Silicon: Towards Analog/Mixed-Signal Design Automation using Surrogate NN Models with Transfer Learning. ICCAD (2021)
Qiaochu Zhang, Shiyu Su, Cheng-Ru Ho, Mike Shuo-Wei Chen
29.4 A Fractional-N Digital MDLL with Background Two-Point DTC Calibration Achieving -60dBc Fractional Spur. ISSCC (2021)
Aoyang Zhang, Mostafa Ayesh, Soumya Mahapatra, Mike Shuo-Wei Chen
A 24-28 GHz Concurrent Harmonic and Subharmonic Tuning Class E/F2, 2/3 Subharmonic Switching Power Amplifier Achieving Peak/PBO Efficiency Enhancement. CICC (2021)
Mohsen Hassanpourghadi, Shiyu Su, Rezwan A. Rasul, Juzheng Liu, Qiaochu Zhang, Mike Shuo-Wei Chen
Circuit Connectivity Inspired Neural Network for Analog Mixed-Signal Functional Modeling. DAC (2021)
Tzu-Fan Wu, Mike Shuo-Wei Chen
16.7 A 40MHz-BW 76.2dB/78.0dB SNDR/DR Noise-Shaping Nonuniform Sampling ADC with Single Phase-Domain Level Crossing and Embedded Nonuniform Digital Signal Processor in 28nm CMOS. ISSCC (2020)
Juzheng Liu, Mohsen Hassanpourghadi, Qiaochu Zhang, Shiyu Su, Mike Shuo-Wei Chen
Transfer Learning with Bayesian Optimization-Aided Sampling for Efficient AMS Circuit Modeling. ICCAD (2020)
Shiyu Su, Mike Shuo-Wei Chen
10.2 A SAW-Less Direct-Digital RF Modulator with Tri-Level Time-Approximation Filter and Reconfigurable Dual-Band Delta-Sigma Modulation. ISSCC (2020)
Jae-Won Nam, Mike Shuo-Wei Chen
A 12.8-Gbaud ADC-Based Wireline Receiver With Embedded IIR Equalizer. IEEE J. Solid State Circuits 55 (3) (2020)
Qiaochu Zhang, Shiyu Su, Juzheng Liu, Mike Shuo-Wei Chen
CEPA: CNN-based Early Performance Assertion Scheme for Analog and Mixed-Signal Circuit Simulation. ICCAD (2020)
Tzu-Fan Wu, Mike Shuo-Wei Chen
A Noise-Shaped VCO-Based Nonuniform Sampling ADC With Phase-Domain Level Crossing. IEEE J. Solid State Circuits 54 (3) (2019)
Aoyang Zhang, Mike Shuo-Wei Chen
A Watt-Level Phase-Interleaved Multi-Subharmonic Switching Digital Power Amplifier Achieving 31.4% Average Drain Efficiency. ISSCC (2019)
Aoyang Zhang, Mike Shuo-Wei Chen
A Subharmonic Switching Digital Power Amplifier for Power Back-Off Efficiency Enhancement. IEEE J. Solid State Circuits 54 (4) (2019)
Aoyang Zhang, Mike Shuo-Wei Chen
A Watt-Level Phase-Interleaved Multi-Subharmonic Switching Digital Power Amplifier. IEEE J. Solid State Circuits 54 (12) (2019)
Mohsen Hassanpourghadi, Mike Shuo-Wei Chen
A 2-way 7.3-bit 10 GS/s Time-based Folding ADC with Passive Pulse-Shrinking Cells. CICC (2019)
Shiyu Su, Mike Shuo-Wei Chen
A 1-5GHz Direct-Digital RF Modulator with an Embedded Time-Approximation Filter Achieving -43dB EVM at 1024 QAM. VLSI Circuits (2019)
Jae-Won Nam, Mike Shuo-Wei Chen
A 12.8-Gbaud ADC-based NRZ/PAM4 Receiver with Embedded Tunable IIR Equalization Filter Achieving 2.43-pJ/b in 65nm CMOS. CICC (2019)
Shiyu Su, Mike Shuo-Wei Chen
A 16b 12GS/S single/dual-rate DAC with successive bandpass delta-sigma modulator achieving <-67dBc IM3 within DC-to-6GHz tunable passbands. ISSCC (2018)
Aoyang Zhang, Mike Shuo-Wei Chen
A Sub-Harmonic Switching Digital Power Amplifier with Hybrid Class-G Operation for Enhancing Power Back-off Efficiency. VLSI Circuits (2018)
Jae-Won Nam, Mohsen Hassanpourghadi, Aoyang Zhang, Mike Shuo-Wei Chen
A 12-Bit 1.6, 3.2, and 6.4 GS/s 4-b/Cycle Time-Interleaved SAR ADC With Dual Reference Shifting and Interpolation. IEEE J. Solid State Circuits 53 (6) (2018)
Cheng-Ru Ho, Mike Shuo-Wei Chen
A fractional-N digital PLL with background-dither-noise-cancellation loop achieving <-62.5dBc worst-case near-carrier fractional spurs in 65nm CMOS. ISSCC (2018)
Tzu-Fan Wu, Mike Shuo-Wei Chen
62dB-DR VCO-based non-uniform sampling ADC with phase-domain level crossing in 65nm CMOS. CICC (2018)
Cheng-Ru Ho, Mike Shuo-Wei Chen
A digital frequency synthesizer with dither-assisted pulling mitigation for simultaneous DCO and reference path coupling. ISSCC (2018)
Mike Shuo-Wei Chen
Evolutions of SAR ADC: From high resolution to high speed regime. CICC (2018)
Shiyu Su, Mike Shuo-Wei Chen
A 16-bit 12-GS/s Single-/Dual-Rate DAC With a Successive Bandpass Delta-Sigma Modulator Achieving <-67-dBc IM3 Within DC to 6-GHz Tunable Passbands. IEEE J. Solid State Circuits 53 (12) (2018)
Tzu-Fan Wu, Cheng-Ru Ho, Mike Shuo-Wei Chen
A Flash-Based Non-Uniform Sampling ADC With Hybrid Quantization Enabling Digital Anti-Aliasing Filter. IEEE J. Solid State Circuits 52 (9) (2017)
Mohsen Hassanpourghadi, Praveen Kumar Sharma, Mike Shuo-Wei Chen
A 6-b, 800-MS/s, 3.62-mW Nyquist Rate AC-Coupled VCO-Based ADC in 65-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2017)
Rezwan A. Rasul, Pedram Teimouri, Mike Shuo-Wei Chen
A time multiplexed network architecture for large-scale neuromorphic computing. MWSCAS (2017)
Cheng-Ru Ho, Mike Shuo-Wei Chen
A Digital PLL With Feedforward Multi-Tone Spur Cancellation Scheme Achieving <-73 dBc Fractional Spur and <-110 dBc Reference Spur in 65 nm CMOS. IEEE J. Solid State Circuits 51 (12) (2016)
Tzu-Fan Wu, Sourya Dey, Mike Shuo-Wei Chen
A Nonuniform Sampling ADC Architecture With Reconfigurable Digital Anti-Aliasing Filter. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2016)
Shiyu Su, Mike Shuo-Wei Chen
A 12-Bit 2 GS/s Dual-Rate Hybrid DAC With Pulse-Error Pre-Distortion and In-Band Noise Cancellation Achieving > 74 dBc SFDR and <-80 dBc IM3 up to 1 GHz in 65 nm CMOS. IEEE J. Solid State Circuits 51 (12) (2016)
Jae-Won Nam, Mohsen Hassanpourghadi, Aoyang Zhang, Mike Shuo-Wei Chen
A 12-bit 1.6 GS/s interleaved SAR ADC with dual reference shifting and interpolation achieving 17.8 fJ/conv-step in 65nm CMOS. VLSI Circuits (2016)
Jae-Won Nam, Mike Shuo-Wei Chen
An Embedded Passive Gain Technique for Asynchronous SAR ADC Achieving 10.2 ENOB 1.36-mW at 95-MS/s in 65 nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2016)
Cheng-Ru Ho, Mike Shuo-Wei Chen
10.5 A digital PLL with feedforward multi-tone spur cancelation loop achieving <-73dBc fractional spur and <-110dBc Reference Spur in 65nm CMOS. ISSCC (2016)
Shiyu Su, Mike Shuo-Wei Chen
27.1 A 12b 2GS/s dual-rate hybrid DAC with pulsed timing-error pre-distortion and in-band noise Cancellation Achieving >74dBc SFDR up to 1GHz in 65nm CMOS. ISSCC (2016)
Cheng-Ru Ho, Mike Shuo-Wei Chen
Interference-induced DCO spur mitigation for digital phase locked loop in 65-nm CMOS. ESSCIRC (2016)
Cheng-Ru Ho, Mike Shuo-Wei Chen
A Fractional-N DPLL With Calibration-Free Multi-Phase Injection-Locked TDC and Adaptive Single-Tone Spur Cancellation Scheme. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2016)
Shiyu Su, Tu-I Tsai, Praveen Kumar Sharma, Mike Shuo-Wei Chen
A 12 bit 1 GS/s Dual-Rate Hybrid DAC With an 8 GS/s Unrolled Pipeline Delta-Sigma Modulator Achieving > 75 dB SFDR Over the Nyquist Band. IEEE J. Solid State Circuits 50 (4) (2015)
Tzu-Fan Wu, Cheng-Ru Ho, Mike Shuo-Wei Chen
A flash-based non-uniform sampling ADC enabling digital anti-aliasing filter in 65nm CMOS. CICC (2015)
Yu Cao, Jyothi Velamala, Ketul Sutaria, Mike Shuo-Wei Chen, Jonathan Ahlbin, Ivan Sanchez Esqueda, Michael Bajura, Michael Fritze
Cross-Layer Modeling and Simulation of Circuit Reliability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (1) (2014)
Shiyu Su, Tu-I Tsai, Praveen Kumar Sharma, Mike Shuo-Wei Chen
A 12-bit hybrid DAC with 8GS/s unrolled pipeline delta-sigma modulator achieving >75dB SFDR over 500MHz in 65nm CMOS. VLSIC (2014)
Praveen Kumar Sharma, Mike Shuo-Wei Chen
A 6b 800MS/s 3.62mW Nyquist AC-coupled VCO-based ADC in 65nm CMOS. CICC (2013)
Jae-Won Nam, David Chiong, Mike Shuo-Wei Chen
A 95-MS/s 11-bit 1.36-mW asynchronous SAR ADC with embedded passive gain in 65nm CMOS. CICC (2013)
Mike Shuo-Wei Chen
Overhead minimization techniques for digital phase-locked loop frequency synthesizer. MWSCAS (2012)
Dylan Hand, Mike Shuo-Wei Chen
A non-uniform sampling ADC architecture with embedded alias-free asynchronous filter. GLOBECOM (2012)
Shahram Abdollahi-Alibeik, David Weber, Hakan Dogan, William W. Si, Burcin Baytekin, Abbas Komijani, Richard Chang, Babak Vakili-Amini, MeeLan Lee, Haitao Gan, Yashar Rajavi, Hirad Samavati, Brian J. Kaczynski, Sang-Min Lee, Sotirios Limotyrakis, Hyunsik Park, Phoebe Chen, Paul Park, Mike Shuo-Wei Chen, Andrew Chang, Yangjin Oh, Jerry Jian-Ming Yang, Eric Chien-Chih Lin, Lalitkumar Nathawad, Keith Onodera, Manolis Terrovitis, Sunetra Mendis, Kai Shi, Srenik S. Mehta, Masoud Zargari, David K. Su
A 65nm dual-band 3-stream 802.11n MIMO WLAN SoC. ISSCC (2011)
Mike Shuo-Wei Chen, David K. Su, Srenik S. Mehta
A Calibration-Free 800 MHz Fractional-N Digital PLL With Embedded TDC. IEEE J. Solid State Circuits 45 (12) (2010)
Mike Shuo-Wei Chen, David K. Su, Srenik S. Mehta
A calibration-free 800MHz fractional-N digital PLL with embedded TDC. ISSCC (2010)
Sundar G. Sankaran, Brian J. Zargari, Lalitkumar Nathawad, Hirad Samavati, Srenik S. Mehta, Alireza Kheirkhahi, Phoebe Chen, Ke Gong, Babak Vakili-Amini, Justin A. Hwang, Mike Shuo-Wei Chen, Manolis Terrovitis, Brian J. Kaczynski, Sotirios Limotyrakis, Michael P. Mack, Haitao Gan, MeeLan Lee, Richard Chang, Hakan Dogan, Shahram Abdollahi-Alibeik, Burcin Baytekin, Keith Onodera, Suni Mendis, Andrew Chang, Yashar Rajavi, Steve Hung-Min Jen, David K. Su, Bruce A. Wooley
Design and implementation of a CMO 802.11n SoC. IEEE Commun. Mag. 47 (4) (2009)
Lalitkumar Nathawad, Masoud Zargari, Hirad Samavati, Srenik S. Mehta, Alireza Kheirkhahi, Phoebe Chen, Ke Gong, Babak Vakili-Amini, Justin A. Hwang, Mike Shuo-Wei Chen, Manolis Terrovitis, Brian J. Kaczynski, Sotirios Limotyrakis, Michael P. Mack, Haitao Gan, MeeLan Lee, Shahram Abdollahi-Alibeik, Burcin Baytekin, Keith Onodera, Sunetra Mendis, Andrew Chang, Steve H. Jen, David K. Su, Bruce A. Wooley
A Dual-Band CMOS MIMO Radio SoC for IEEE 802.11n Wireless LAN. ISSCC (2008)
Masoud Zargari, Lalitkumar Nathawad, Hirad Samavati, Srenik S. Mehta, Alireza Kheirkhahi, Phoebe Chen, Ke Gong, Babak Vakili-Amini, Justin A. Hwang, Mike Shuo-Wei Chen, Manolis Terrovitis, Brian J. Kaczynski, Sotirios Limotyrakis, Michael P. Mack, Haitao Gan, MeeLan Lee, Richard Chang, Hakan Dogan, Shahram Abdollahi-Alibeik, Burcin Baytekin, Keith Onodera, Suni Mendis, Andrew Chang, Yashar Rajavi, Steve Hung-Min Jen, David K. Su, Bruce A. Wooley
A Dual-Band CMOS MIMO Radio SoC for IEEE 802.11n Wireless LAN. IEEE J. Solid State Circuits 43 (12) (2008)
Andrew Fort, Mike Shuo-Wei Chen, Robert W. Brodersen, Claude Desset, Piet Wambacq, Leo Van Biesen
Impact of Sampling Jitter on Mostly-Digital Architectures for UWB Bio-Medical Applications. ICC (2007)
Mike Shuo-Wei Chen, Robert W. Brodersen
Digital Complex Signal Processing Techniques for Impulse Radio. GLOBECOM (2006)
Danijela Cabric, Mike Shuo-Wei Chen, David A. Sobel, Stanley Wang, Jing Yang, Robert W. Brodersen
Novel Radio Architectures for UWB, 60 GHz, and Cognitive Wireless Systems. EURASIP J. Wirel. Commun. Netw. 2006 (2006)
Mike Shuo-Wei Chen, Robert W. Brodersen
A 6b 600MS/s 5.3mW Asynchronous ADC in 0.13µm CMOS. ISSCC (2006)
Mike Shuo-Wei Chen, Robert W. Brodersen
A Subsampling UWB Impulse Radio Architecture Utilizing Analytic Signaling. IEICE Trans. Electron. (6) (2005)
Danijela Cabric, Mike Shuo-Wei Chen, David A. Sobel, Jing Yang, Robert W. Brodersen
Future wireless systems: UWB, 60GHz, and cognitive radios. CICC (2005)
Mike Shuo-Wei Chen, Robert W. Brodersen
A subsampling UWB radio architecture by analytic signaling. ICASSP (4) (2004)