Login / Signup
A 12-bit 1.6 GS/s interleaved SAR ADC with dual reference shifting and interpolation achieving 17.8 fJ/conv-step in 65nm CMOS.
Jae-Won Nam
Mohsen Hassanpourghadi
Aoyang Zhang
Mike Shuo-Wei Chen
Published in:
VLSI Circuits (2016)
Keyphrases
</>
analog to digital converter
nm technology
random access memory
high speed
post processing
multiscale
infrared
power consumption
single chip
table lookup