Jae-Won Nam

Publication Activity (10 Years)

Years Active: 2009-2023
Publications (10 Years): 15

Top Topics

Cmos Technology

Integer Programming

Dantzig Wolfe Decomposition

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Jin-Won Hyun, Jae-Won Nam
Regression Model-based VCO Design Optimization Technique. ICEIC (2023)
Jin-Won Hyun, Jae-Won Nam
AMS Circuit Design Optimization Technique Based on ANN Regression Model With VAE Structure. IEEE Access 11 (2023)
Dana Kim, Jong-Phil Hong, Jiwon Lee, Jae-Won Nam
High-Speed Light Detection Sensor for Hardware Security in Standard CMOS Technology. IEEE Trans. Circuits Syst. II Express Briefs 70 (10) (2023)
Jae-Yun Park, Su-Hyeon Kim, Hyunyoung Yoo, Jae-Won Nam
Analysis of Quarter Method Applied ROM-Based DDFS Architecture. IEEE Access 11 (2023)
Seungmo Kim, Yeonho Jeong, Jae-Won Nam
Optimizing EV Chargers Location via Integer Programming. CoRR (2023)
Jae-Won Nam, Ju-Hyeok Ahn, Jong-Phil Hong
Compact SRAM-Based PUF Chip Employing Body Voltage Control Technique. IEEE Access 10 (2022)
Young-Kyun Cho, Jae-Won Nam, Sang-Won Lee
A Low-Power Class-C Voltage-Controlled Oscillator With Robust Start-Up and Compact High-Q Capacitor Array. IEEE Trans. Circuits Syst. II Express Briefs 69 (3) (2022)
Jae-Won Nam, Youn Kyu Lee
Machine-Learning based Analog and Mixed-signal Circuit Design and Optimization. ICOIN (2021)
Soowang Park, Jae-Won Nam, Sandeep K. Gupta
HW-BCP: A Custom Hardware Accelerator for SAT Suitable for Single Chip Implementation for Large Benchmarks. ASP-DAC (2021)
Hee won Kwon, Jae-Won Nam, Joongheon Kim, Youn Kyu Lee
Generative Adversarial Attacks on Fingerprint Recognition Systems. ICOIN (2021)
Jae-Won Nam, Mike Shuo-Wei Chen
A 12.8-Gbaud ADC-Based Wireline Receiver With Embedded IIR Equalizer. IEEE J. Solid State Circuits 55 (3) (2020)
Jae-Won Nam, Mike Shuo-Wei Chen
A 12.8-Gbaud ADC-based NRZ/PAM4 Receiver with Embedded Tunable IIR Equalization Filter Achieving 2.43-pJ/b in 65nm CMOS. CICC (2019)
Jae-Won Nam, Mohsen Hassanpourghadi, Aoyang Zhang, Mike Shuo-Wei Chen
A 12-Bit 1.6, 3.2, and 6.4 GS/s 4-b/Cycle Time-Interleaved SAR ADC With Dual Reference Shifting and Interpolation. IEEE J. Solid State Circuits 53 (6) (2018)
Jae-Won Nam, Mohsen Hassanpourghadi, Aoyang Zhang, Mike Shuo-Wei Chen
A 12-bit 1.6 GS/s interleaved SAR ADC with dual reference shifting and interpolation achieving 17.8 fJ/conv-step in 65nm CMOS. VLSI Circuits (2016)
Jae-Won Nam, Mike Shuo-Wei Chen
An Embedded Passive Gain Technique for Asynchronous SAR ADC Achieving 10.2 ENOB 1.36-mW at 95-MS/s in 65 nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2016)
Jae-Won Nam, David Chiong, Mike Shuo-Wei Chen
A 95-MS/s 11-bit 1.36-mW asynchronous SAR ADC with embedded passive gain in 65nm CMOS. CICC (2013)
Young-Deuk Jeon, Jae-Won Nam, Kwi-Dong Kim, Tae Moon Roh, Jong-Kee Kwon
A Dual-Channel Pipelined ADC With Sub-ADC Based on Flash-SAR Architecture. IEEE Trans. Circuits Syst. II Express Briefs (11) (2012)
Jae-Won Nam, Young-Deuk Jeon, Young-Kyun Cho, Jong-Kee Kwon
A 12-bit 200-MS/s pipelined A/D converter with sampling skew reduction technique. Microelectron. J. 42 (11) (2011)
Young-Kyun Cho, Young-Deuk Jeon, Jae-Won Nam, Jong-Kee Kwon
A 10-bit 30-MS/s successive approximation register analog-to-digital converter for low-power sub-sampling applications. Microelectron. J. 42 (12) (2011)
Jae-Won Nam, Young-Deuk Jeon, Seok-Ju Yun, Tae Moon Roh, Jong-Kee Kwon
A 12-bit 100-MS/s pipelined ADC in 45-nm CMOS. ISOCC (2011)
Young-Kyun Cho, Young-Deuk Jeon, Jae-Won Nam, Jong-Kee Kwon
A 9-bit 80 MS/s Successive Approximation Register Analog-to-Digital Converter With a Capacitor Reduction Technique. IEEE Trans. Circuits Syst. II Express Briefs (7) (2010)
Young-Deuk Jeon, Young-Kyun Cho, Jae-Won Nam, Kwi-Dong Kim, Woo-Yol Lee, Kuk-Tae Hong, Jong-Kee Kwon
10b 204MS/s pipelined SAR ADC in 65nm CMOS. CICC (2010)
Jae-Won Nam, Young-Deuk Jeon, Young-Kyun Cho, Sang-Gug Lee, Jong-Kee Kwon
A 2.85mW 0.12mm2 1.0V 11-bit 20-MS/s algorithmic ADC in 65nm CMOS. ESSCIRC (2009)