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27.1 A 12b 2GS/s dual-rate hybrid DAC with pulsed timing-error pre-distortion and in-band noise Cancellation Achieving >74dBc SFDR up to 1GHz in 65nm CMOS.
Shiyu Su
Mike Shuo-Wei Chen
Published in:
ISSCC (2016)
Keyphrases
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noise cancellation
input output
high speed
frequency band
estimation error
adaptive algorithms
error propagation
cmos technology
adaptive filter
noise reduction
power consumption
noise removal
low power
restoration algorithm
silicon on insulator
adaptive filtering