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A 12-Bit 2 GS/s Dual-Rate Hybrid DAC With Pulse-Error Pre-Distortion and In-Band Noise Cancellation Achieving > 74 dBc SFDR and <-80 dBc IM3 up to 1 GHz in 65 nm CMOS.
Shiyu Su
Mike Shuo-Wei Chen
Published in:
IEEE J. Solid State Circuits (2016)
Keyphrases
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noise cancellation
input output
high speed
frequency band
estimation error
error propagation
power consumption
nm technology
adaptive algorithms
noise reduction
adaptive filter
random access memory
silicon on insulator
neural network
low power