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Aging-Aware Timing Model of CMOS Inverter: Path Level Timing Performance and Its Impact on the Logical Effort.

Lomash Chandra AcharyaArvind Kumar SharmaNeeraj MishraKhoirom Johnson SinghMahipal DargupallyNayakanti Sai ShabarishAjoy MandalVenkatraman RamakrishnanSudeb DasguptaAnand Bulusu
Published in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2023)
Keyphrases
  • probabilistic model
  • management system
  • neural network
  • high level
  • parameter estimation
  • computational model
  • simulation model
  • formal model
  • data sets
  • theoretical framework
  • statistical model