Bulusu Anand

Publication Activity (10 Years)

Years Active: 2011-2022
Publications (10 Years): 5

Top Topics

Mobile Handheld Devices

Equivalent Circuit

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

Microelectron. Reliab.

Publications

Lalit Mohan Dani, Neeraj Mishra, Bulusu Anand
A Variation Aware Jitter Estimation Methodology in ROs Considering Over/Undershoots in NTV Regime. IEEE Trans. Circuits Syst. II Express Briefs 69 (3) (2022)
Shashank Banchhor, Nitanshu Chauhan, Aditya Doneria, Bulusu Anand
Gain Stabilization Methodology for FinFET Amplifiers Considering Self-Heating Effect. VLSI Design (2021)
Lalit Dani, Neeraj Mishra, Bulusu Anand
MOS Varactor RO Architectures in Near Threshold Regime Using Forward Body Biasing Techniques. VLSI Design (2019)
Sayyaparaju Sagar Varma, Arvind Kumar Sharma, Bulusu Anand
An efficient methodology to characterize the TSPC flip flop setup time for static timing analysis. SMACD (2016)
Baljit Kaur, Arvind Kumar Sharma, Naushad Alam, S. K. Manhas, Bulusu Anand
A variation aware timing model for a 2-input NAND gate and its use in sub-65 nm CMOS standard cell characterization. Microelectron. J. 53 (2016)
Sudeb Dasgupta, Bulusu Anand
Tutorial T6: FinFET Device Circuit Co-design: Issues and Challenges. VLSI Design (2015)
Arvind Kumar Sharma, Yogendra Sharma, Sudeb Dasgupta, Bulusu Anand
Efficient static D-latch standard cell characterization using a novel setup time model. ISQED (2015)
Yogesh Chaurasiya, Surabhi Bhargava, Arvind Kumar Sharma, Baljit Kaur, Bulusu Anand
Timing model for two stage buffer and its application in ECSM characterization. VDAT (2015)
Baljit Kaur, Naushad Alam, S. K. Manhas, Bulusu Anand
Efficient ECSM Characterization Considering Voltage, Temperature, and Mechanical Stress Variability. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2014)
Naushad Alam, Bulusu Anand, Sudeb Dasgupta
An Analytical Delay Model for Mechanical Stress Induced Systematic Variability Analysis in Nanoscale Circuit Design. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2014)
Bijay Kumar Dalai, N. Karnnan, Arvind Kumar Sharma, Bulusu Anand
An empirical delta delay model for highly scaled CMOS inverter considering Well Proximity Effect. VDAT (2014)
Baljit Kaur, Sandeep Miryala, S. K. Manhas, Bulusu Anand
An efficient method for ECSM characterization of CMOS inverter in nanometer range technologies. ISQED (2013)
Naushad Alam, Bulusu Anand, Sudeb Dasgupta
The impact of process-induced mechanical stress in narrow width devices and variable-taper CMOS buffer design. Microelectron. Reliab. 53 (5) (2013)
Naushad Alam, Bulusu Anand, Sudeb Dasgupta
The impact of process-induced mechanical stress on CMOS buffer design using multi-fingered devices. Microelectron. Reliab. 53 (3) (2013)
Naushad Alam, Bulusu Anand, Sudeb Dasgupta
Impact of Dummy Poly on the Process-Induced Mechanical Stress Enhanced Circuit Performance. VDAT (2012)
Naushad Alam, Bulusu Anand, Sudeb Dasgupta
The Impact of Process-Induced Mechanical Stress in Narrow Width Devices and Circuit Design Issues. ISED (2012)
Naushad Alam, Bulusu Anand, Sudeb Dasgupta
Process induced mechanical stress aware poly-pitch optimization for enhanced circuit performance. ISQED (2012)
Baljit Kaur, Sandeep Vundavalli, S. K. Manhas, Sudeb Dasgupta, Bulusu Anand
An accurate current source model for CMOS based combinational logic cell. ISQED (2012)
Sandeep Miryala, Baljit Kaur, Bulusu Anand, Sanjeev Manhas
Efficient nanoscale VLSI standard cell library characterization using a novel delay model. ISQED (2011)