Vivek Asthana

Publication Activity (10 Years)

Years Active: 2013-2022
Publications (10 Years): 2

Top Topics

Dynamic Random Access Memory

Power Reduction

Top Venues

Publications

R. Mathur, M. Kumar, Vivek Asthana, S. Aggarwal, S. Gupta, D. Wanjul, A. Baradia, S. Thota, P. Jain, B. Zheng, A. Cubeta, S. Thyagarajan, A. Chen, Y. K. Chong
5GHz SRAM for High-Performance Compute Platform in 5nm CMOS. CICC (2022)
Vivek Asthana, M. Jagadesh Kumar, Ayush Kulshrestha, Munish Kumar, Saikat Kumar Banik, Shruti Aggarwal
0.25pA/Bit Ultra-Low-Leakage 6T Single-Port SRAM on 22nm Bulk Process for IoT Applications. ISCAS (2020)
Parmanand Singh, Vivek Asthana, Radhakrishnan Sithanandam, Anand Bulusu, Sudeb Dasgupta
Analytical Modeling of Sub-onset Current of Tunnel Field Effect Transistor. VLSI Design (2014)
Vivek Asthana, Malathi Kar, Jean Jimenez, Jean-Philippe Noel, Sébastien Haendler, Philippe Galy
Circuit optimization of 4T, 6T, 8T, 10T SRAM bitcells in 28nm UTBB FD-SOI technology using back-gate bias control. ESSCIRC (2013)
Vivek Asthana, Malathi Kar, Jean Jimenez, Sébastien Haendler, Philippe Galy
6T SRAM performance and power gain using double gate MOS in 28nm FDSOI technology. ICICDT (2013)