Circuit optimization of 4T, 6T, 8T, 10T SRAM bitcells in 28nm UTBB FD-SOI technology using back-gate bias control.
Vivek AsthanaMalathi KarJean JimenezJean-Philippe NoelSébastien HaendlerPhilippe GalyPublished in: ESSCIRC (2013)
Keyphrases
- cmos technology
- silicon on insulator
- low power
- power consumption
- nm technology
- low voltage
- power dissipation
- parallel processing
- dynamic random access memory
- high speed
- low cost
- optimization method
- metal oxide semiconductor
- control system
- image sensor
- optimization problems
- embedded dram
- global optimization
- data acquisition
- power management
- neural network
- optimization algorithm
- power reduction
- genetic algorithm