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Design optimization Using Symmetric/Asymmetric Spacer for 14 nm Multi-Fin Tri-gate Fin-FET for Mid-Band 5G Applications.
Jyoti Patel
Shashank Banchhor
Surila Guglani
Avirup Dasgupta
Sourajeet Roy
Anand Bulusu
Sudeb Dasgupta
Published in:
VLSID (2022)
Keyphrases
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