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A 1.2 pJ/cycle KHz Timer Circuit for Heavily Duty-Cycled Systems.
R. R. Manikandan
Vipul Kumar Singhal
Rajat Chauhan
Vinod Menezes
Mahesh Mehendale
Published in:
VLSI Design (2018)
Keyphrases
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computer systems
real time
case study
data structure
electronic circuits
computer vision
database systems
multiscale
multi agent
digital libraries
high speed
complex systems