A 1.2 pJ/cycle KHz Timer Circuit for Heavily Duty-Cycled Systems.

R. R. Manikandan Vipul Kumar Singhal Rajat Chauhan Vinod Menezes Mahesh Mehendale

Published in: VLSI Design (2018)

Keyphrases

computer systems
real time
case study
data structure
electronic circuits
computer vision
database systems
multiscale
multi agent
digital libraries
high speed
complex systems