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Optimization of 1.8V I/O circuits for performance, reliability at the 100nm technology node.
Vinod Menezes
C. B. Keshav
Sushil Gupta
M. Roopashree
S. Krishnan
A. Amerasekera
G. Palau
Published in:
VLSI Design (2003)
Keyphrases
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nm technology
optimization algorithm
power dissipation
input output
optimization process
power consumption
high speed
optimization problems
neural network
relational databases
file system
low power
graph structure
analog circuits